/linux/drivers/clk/hisilicon/ |
H A D | clk-hi3670.c | 81 CLK_SET_RATE_PARENT, 0x0, 0, 0, }, 83 CLK_SET_RATE_PARENT, 0x0, 3, 0, }, 85 CLK_SET_RATE_PARENT, 0x0, 27, 0, }, 87 CLK_SET_RATE_PARENT, 0x460, 16, 0, }, 89 CLK_SET_RATE_PARENT, 0x460, 18, 0, }, 91 CLK_SET_RATE_PARENT, 0x460, 20, 0, }, 93 CLK_SET_RATE_PARENT, 0x410, 27, 0, }, 95 CLK_SET_RATE_PARENT, 0x410, 28, 0, }, 97 CLK_SET_RATE_PARENT, 0x410, 26, 0, }, 99 CLK_SET_RATE_PARENT, 0x410, 30, 0, }, [all …]
|
H A D | clk-hi3660.c | 53 CLK_SET_RATE_PARENT, 0x0, 0, 0, }, 55 CLK_SET_RATE_PARENT, 0x0, 21, 0, }, 57 CLK_SET_RATE_PARENT, 0x0, 30, 0, }, 59 CLK_SET_RATE_PARENT, 0x0, 31, 0, }, 61 CLK_SET_RATE_PARENT, 0x10, 0, 0, }, 63 CLK_SET_RATE_PARENT, 0x10, 1, 0, }, 65 CLK_SET_RATE_PARENT, 0x10, 2, 0, }, 67 CLK_SET_RATE_PARENT, 0x10, 3, 0, }, 69 CLK_SET_RATE_PARENT, 0x10, 4, 0, }, 71 CLK_SET_RATE_PARENT, 0x10, 5, 0, }, [all …]
|
H A D | clk-hi6220.c | 52 …{ HI6220_WDT0_PCLK, "wdt0_pclk", "ref32k", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 12,… 53 …{ HI6220_WDT1_PCLK, "wdt1_pclk", "ref32k", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 13,… 54 …{ HI6220_WDT2_PCLK, "wdt2_pclk", "ref32k", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 14,… 55 …{ HI6220_TIMER0_PCLK, "timer0_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 15,… 56 …{ HI6220_TIMER1_PCLK, "timer1_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 16,… 57 …{ HI6220_TIMER2_PCLK, "timer2_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 17,… 58 …{ HI6220_TIMER3_PCLK, "timer3_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 18,… 59 …{ HI6220_TIMER4_PCLK, "timer4_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 19,… 60 …{ HI6220_TIMER5_PCLK, "timer5_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 20,… 61 …{ HI6220_TIMER6_PCLK, "timer6_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 21,… [all …]
|
H A D | clk-hi3620.c | 85 …{ HI3620_TIMER0_MUX, "timer0_mux", timer0_mux_p, ARRAY_SIZE(timer0_mux_p), CLK_SET_RATE_PARENT, 0,… 86 …{ HI3620_TIMER1_MUX, "timer1_mux", timer1_mux_p, ARRAY_SIZE(timer1_mux_p), CLK_SET_RATE_PARENT, 0,… 87 …{ HI3620_TIMER2_MUX, "timer2_mux", timer2_mux_p, ARRAY_SIZE(timer2_mux_p), CLK_SET_RATE_PARENT, 0,… 88 …{ HI3620_TIMER3_MUX, "timer3_mux", timer3_mux_p, ARRAY_SIZE(timer3_mux_p), CLK_SET_RATE_PARENT, 0,… 89 …{ HI3620_TIMER4_MUX, "timer4_mux", timer4_mux_p, ARRAY_SIZE(timer4_mux_p), CLK_SET_RATE_PARENT, 0x… 90 …{ HI3620_TIMER5_MUX, "timer5_mux", timer5_mux_p, ARRAY_SIZE(timer5_mux_p), CLK_SET_RATE_PARENT, 0x… 91 …{ HI3620_TIMER6_MUX, "timer6_mux", timer6_mux_p, ARRAY_SIZE(timer6_mux_p), CLK_SET_RATE_PARENT, 0x… 92 …{ HI3620_TIMER7_MUX, "timer7_mux", timer7_mux_p, ARRAY_SIZE(timer7_mux_p), CLK_SET_RATE_PARENT, 0x… 93 …{ HI3620_TIMER8_MUX, "timer8_mux", timer8_mux_p, ARRAY_SIZE(timer8_mux_p), CLK_SET_RATE_PARENT, 0x… 94 …{ HI3620_TIMER9_MUX, "timer9_mux", timer9_mux_p, ARRAY_SIZE(timer9_mux_p), CLK_SET_RATE_PARENT, 0x… [all …]
|
H A D | crg-hi3798cv200.c | 76 CLK_SET_RATE_PARENT, 0xa0, 8, 3, 0, mmc_mux_table, }, 79 CLK_SET_RATE_PARENT, 0x188, 2, 2, 0, comphy_mux_table, }, 82 CLK_SET_RATE_PARENT, 0x188, 10, 2, 0, comphy_mux_table, }, 84 ARRAY_SIZE(sdio_mux_p), CLK_SET_RATE_PARENT, 93 CLK_SET_RATE_PARENT, 0xa0, 12, 3, mmc_phase_degrees, 96 CLK_SET_RATE_PARENT, 0xa0, 16, 3, mmc_phase_degrees, 103 CLK_SET_RATE_PARENT, 0x68, 4, 0, }, 106 CLK_SET_RATE_PARENT, 0x6C, 4, 0, }, 108 CLK_SET_RATE_PARENT, 0x6C, 8, 0, }, 110 CLK_SET_RATE_PARENT, 0x6C, 12, 0, }, [all …]
|
H A D | clk-hi3559a.c | 142 CLK_SET_RATE_PARENT, 0x170, 2, 3, 0, fmc_mux_table, 146 CLK_SET_RATE_PARENT, 0x1a8, 24, 3, 0, mmc_mux_table, 150 CLK_SET_RATE_PARENT, 0x1ec, 24, 3, 0, mmc_mux_table, 155 CLK_SET_RATE_PARENT, 0x214, 24, 3, 0, mmc_mux_table, 160 CLK_SET_RATE_PARENT, 0x23c, 24, 3, 0, mmc_mux_table, 165 CLK_SET_RATE_PARENT, 0xe8, 3, 1, 0, sysapb_mux_table 170 CLK_SET_RATE_PARENT, 0xe8, 0, 1, 0, sysbus_mux_table 175 CLK_SET_RATE_PARENT, 0x198, 28, 2, 0, uart_mux_table 180 CLK_SET_RATE_PARENT, 0xe4, 0, 2, 0, a73_clksel_mux_table 187 CLK_SET_RATE_PARENT, 0x170, 1, 0, [all …]
|
H A D | clk-hix5hd2.c | 60 CLK_SET_RATE_PARENT, 0x5c, 8, 3, 0, sfc_mux_table, }, 62 CLK_SET_RATE_PARENT, 0xa0, 8, 2, 0, sdio_mux_table, }, 64 CLK_SET_RATE_PARENT, 0x9c, 8, 2, 0, sdio_mux_table, }, 67 CLK_SET_RATE_PARENT, 0x120, 8, 2, 0, fephy_mux_table, }, 73 CLK_SET_RATE_PARENT, 0x5c, 0, 0, }, 75 CLK_SET_RATE_PARENT, 0x5c, 4, CLK_GATE_SET_TO_DISABLE, }, 78 CLK_SET_RATE_PARENT, 0x9c, 0, 0, }, 80 CLK_SET_RATE_PARENT, 0x9c, 1, 0, }, 82 CLK_SET_RATE_PARENT, 0x9c, 4, CLK_GATE_SET_TO_DISABLE, }, 85 CLK_SET_RATE_PARENT, 0xa0, 0, 0, }, [all …]
|
H A D | crg-hi3516cv300.c | 70 CLK_SET_RATE_PARENT, 0xe4, 19, 1, 0, uart_mux_table, }, 72 CLK_SET_RATE_PARENT, 0xc0, 2, 3, 0, fmc_mux_table, }, 74 CLK_SET_RATE_PARENT, 0xc4, 4, 2, 0, mmc_mux_table, }, 76 CLK_SET_RATE_PARENT, 0xc4, 12, 2, 0, mmc_mux_table, }, 78 CLK_SET_RATE_PARENT, 0xc4, 20, 2, 0, mmc2_mux_table, }, 80 CLK_SET_RATE_PARENT, 0xc8, 4, 2, 0, mmc_mux_table, }, 82 CLK_SET_RATE_PARENT, 0x38, 2, 2, 0, pwm_mux_table, }, 87 { HI3516CV300_UART0_CLK, "clk_uart0", "uart_mux", CLK_SET_RATE_PARENT, 89 { HI3516CV300_UART1_CLK, "clk_uart1", "uart_mux", CLK_SET_RATE_PARENT, 91 { HI3516CV300_UART2_CLK, "clk_uart2", "uart_mux", CLK_SET_RATE_PARENT, [all …]
|
/linux/drivers/clk/mmp/ |
H A D | clk-of-pxa168.c | 125 CLK_SET_RATE_PARENT, in pxa168_pll_init() 163 …{0, "twsi0_mux", twsi_parent_names, ARRAY_SIZE(twsi_parent_names), CLK_SET_RATE_PARENT, APBC_TWSI0… 164 …{0, "twsi1_mux", twsi_parent_names, ARRAY_SIZE(twsi_parent_names), CLK_SET_RATE_PARENT, APBC_TWSI1… 165 …{0, "kpc_mux", kpc_parent_names, ARRAY_SIZE(kpc_parent_names), CLK_SET_RATE_PARENT, APBC_KPC, 4, 3… 166 …{0, "pwm0_mux", pwm_parent_names, ARRAY_SIZE(pwm_parent_names), CLK_SET_RATE_PARENT, APBC_PWM0, 4,… 167 …{0, "pwm1_mux", pwm_parent_names, ARRAY_SIZE(pwm_parent_names), CLK_SET_RATE_PARENT, APBC_PWM1, 4,… 168 …{0, "pwm2_mux", pwm_parent_names, ARRAY_SIZE(pwm_parent_names), CLK_SET_RATE_PARENT, APBC_PWM2, 4,… 169 …{0, "pwm3_mux", pwm_parent_names, ARRAY_SIZE(pwm_parent_names), CLK_SET_RATE_PARENT, APBC_PWM3, 4,… 170 …{0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART0… 171 …{0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART1… [all …]
|
H A D | clk-of-mmp2.c | 175 …{MMP2_CLK_I2S0, "i2s0_clk", "i2s0_pll", CLK_SET_RATE_PARENT, MPMU_ACGR, 0x200000, 0x200000, 0x0, 0… 176 …{MMP2_CLK_I2S1, "i2s1_clk", "i2s1_pll", CLK_SET_RATE_PARENT, MPMU_ACGR, 0x100000, 0x100000, 0x0, 0… 201 CLK_SET_RATE_PARENT, in mmp2_main_clk_init() 208 CLK_SET_RATE_PARENT, in mmp2_main_clk_init() 213 CLK_SET_RATE_PARENT, in mmp2_main_clk_init() 239 …{0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART0… 240 …{0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART1… 241 …{0, "uart2_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART2… 242 …{0, "uart3_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART3… 243 …{0, "ssp0_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP0, 4,… [all …]
|
H A D | clk-of-pxa910.c | 105 CLK_SET_RATE_PARENT, in pxa910_pll_init() 128 …{0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART0… 129 …{0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART1… 130 …{0, "ssp0_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP0, 4,… 131 …{0, "ssp1_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP1, 4,… 132 …{0, "timer0_mux", timer_parent_names, ARRAY_SIZE(timer_parent_names), CLK_SET_RATE_PARENT, APBC_TI… 133 …{0, "timer1_mux", timer_parent_names, ARRAY_SIZE(timer_parent_names), CLK_SET_RATE_PARENT, APBC_TI… 137 …{0, "uart2_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBCP_UART… 141 …{PXA910_CLK_TWSI0, "twsi0_clk", "pll1_13_1_5", CLK_SET_RATE_PARENT, APBC_TWSI0, 0x3, 0x3, 0x0, 0, … 142 …{PXA910_CLK_GPIO, "gpio_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_GPIO, 0x3, 0x3, 0x0, 0, &reset_l… [all …]
|
H A D | clk-of-pxa1928.c | 80 CLK_SET_RATE_PARENT, in pxa1928_pll_init() 99 …{0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, PXA1928_CL… 100 …{0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, PXA1928_CL… 101 …{0, "uart2_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, PXA1928_CL… 102 …{0, "uart3_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, PXA1928_CL… 103 …{0, "ssp0_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, PXA1928_CLK_S… 104 …{0, "ssp1_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, PXA1928_CLK_S… 108 …{PXA1928_CLK_TWSI0, "twsi0_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_TWSI0 * 4, 0x3, 0x3, 0… 109 …{PXA1928_CLK_TWSI1, "twsi1_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_TWSI1 * 4, 0x3, 0x3, 0… 110 …{PXA1928_CLK_TWSI2, "twsi2_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_TWSI2 * 4, 0x3, 0x3, 0… [all …]
|
H A D | clk-pxa1908-apbc.c | 47 {PXA1908_CLK_TWSI0, "twsi0_clk", "pll1_32", CLK_SET_RATE_PARENT, APBC_TWSI0, 0x7, 3, 0, 0, NULL}, 48 {PXA1908_CLK_TWSI1, "twsi1_clk", "pll1_32", CLK_SET_RATE_PARENT, APBC_TWSI1, 0x7, 3, 0, 0, NULL}, 49 {PXA1908_CLK_TWSI3, "twsi3_clk", "pll1_32", CLK_SET_RATE_PARENT, APBC_TWSI3, 0x7, 3, 0, 0, NULL}, 50 {PXA1908_CLK_GPIO, "gpio_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_GPIO, 0x7, 3, 0, 0, NULL}, 51 …{PXA1908_CLK_KPC, "kpc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_KPC, 0x7, 3, 0, MMP_CLK_GATE_NEED_… 52 …{PXA1908_CLK_RTC, "rtc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_RTC, 0x87, 0x83, 0, MMP_CLK_GATE_N… 53 …{PXA1908_CLK_PWM0, "pwm0_clk", "pwm01_apb_share", CLK_SET_RATE_PARENT, APBC_PWM0, 0x2, 2, 0, 0, &p… 54 …{PXA1908_CLK_PWM1, "pwm1_clk", "pwm01_apb_share", CLK_SET_RATE_PARENT, APBC_PWM1, 0x6, 2, 0, 0, NU… 55 …{PXA1908_CLK_PWM2, "pwm2_clk", "pwm23_apb_share", CLK_SET_RATE_PARENT, APBC_PWM2, 0x2, 2, 0, 0, NU… 56 …{PXA1908_CLK_PWM3, "pwm3_clk", "pwm23_apb_share", CLK_SET_RATE_PARENT, APBC_PWM3, 0x6, 2, 0, 0, NU… [all …]
|
/linux/drivers/clk/rockchip/ |
H A D | clk-rk3308.c | 199 MUX(0, "clk_uart0_mux", mux_uart0_p, CLK_SET_RATE_PARENT, 203 MUX(0, "clk_uart1_mux", mux_uart1_p, CLK_SET_RATE_PARENT, 207 MUX(0, "clk_uart2_mux", mux_uart2_p, CLK_SET_RATE_PARENT, 211 MUX(0, "clk_uart3_mux", mux_uart3_p, CLK_SET_RATE_PARENT, 215 MUX(0, "clk_uart4_mux", mux_uart4_p, CLK_SET_RATE_PARENT, 219 MUX(0, "dclk_vop_mux", mux_dclk_vop_p, CLK_SET_RATE_PARENT, 223 MUX(SCLK_RTC32K, "clk_rtc32k", mux_rtc32k_p, CLK_SET_RATE_PARENT, 227 MUX(0, "clk_pdm_mux", mux_pdm_p, CLK_SET_RATE_PARENT, 231 MUX(SCLK_I2S0_8CH_TX_MUX, "clk_i2s0_8ch_tx_mux", mux_i2s0_8ch_tx_p, CLK_SET_RATE_PARENT, 235 MUX(SCLK_I2S0_8CH_RX_MUX, "clk_i2s0_8ch_rx_mux", mux_i2s0_8ch_rx_p, CLK_SET_RATE_PARENT, [all …]
|
/linux/drivers/clk/qcom/ |
H A D | dispcc-sm8450.c | 303 .flags = CLK_SET_RATE_PARENT, 323 .flags = CLK_SET_RATE_PARENT, 338 .flags = CLK_SET_RATE_PARENT, 353 .flags = CLK_SET_RATE_PARENT, 367 .flags = CLK_SET_RATE_PARENT, 382 .flags = CLK_SET_RATE_PARENT, 397 .flags = CLK_SET_RATE_PARENT, 412 .flags = CLK_SET_RATE_PARENT, 426 .flags = CLK_SET_RATE_PARENT, 441 .flags = CLK_SET_RATE_PARENT, [all …]
|
H A D | camcc-sa8775p.c | 101 .flags = CLK_SET_RATE_PARENT, 124 .flags = CLK_SET_RATE_PARENT, 201 .flags = CLK_SET_RATE_PARENT, 251 .flags = CLK_SET_RATE_PARENT, 301 .flags = CLK_SET_RATE_PARENT, 393 .flags = CLK_SET_RATE_PARENT, 413 .flags = CLK_SET_RATE_PARENT, 428 .flags = CLK_SET_RATE_PARENT, 443 .flags = CLK_SET_RATE_PARENT, 458 .flags = CLK_SET_RATE_PARENT, [all …]
|
H A D | dispcc-sm8550.c | 293 .flags = CLK_SET_RATE_PARENT, 313 .flags = CLK_SET_RATE_PARENT, 328 .flags = CLK_SET_RATE_PARENT, 343 .flags = CLK_SET_RATE_PARENT, 357 .flags = CLK_SET_RATE_PARENT, 372 .flags = CLK_SET_RATE_PARENT, 387 .flags = CLK_SET_RATE_PARENT, 402 .flags = CLK_SET_RATE_PARENT, 416 .flags = CLK_SET_RATE_PARENT, 431 .flags = CLK_SET_RATE_PARENT, [all …]
|
H A D | camcc-sm8250.c | 89 .flags = CLK_SET_RATE_PARENT, 112 .flags = CLK_SET_RATE_PARENT, 163 .flags = CLK_SET_RATE_PARENT, 214 .flags = CLK_SET_RATE_PARENT, 265 .flags = CLK_SET_RATE_PARENT, 316 .flags = CLK_SET_RATE_PARENT, 413 .flags = CLK_SET_RATE_PARENT, 435 .flags = CLK_SET_RATE_PARENT, 456 .flags = CLK_SET_RATE_PARENT, 471 .flags = CLK_SET_RATE_PARENT, [all …]
|
H A D | camcc-sm8650.c | 108 .flags = CLK_SET_RATE_PARENT, 131 .flags = CLK_SET_RATE_PARENT, 185 .flags = CLK_SET_RATE_PARENT, 266 .flags = CLK_SET_RATE_PARENT, 320 .flags = CLK_SET_RATE_PARENT, 374 .flags = CLK_SET_RATE_PARENT, 428 .flags = CLK_SET_RATE_PARENT, 482 .flags = CLK_SET_RATE_PARENT, 536 .flags = CLK_SET_RATE_PARENT, 590 .flags = CLK_SET_RATE_PARENT, [all …]
|
H A D | dispcc-sc8280xp.c | 435 .flags = CLK_SET_RATE_PARENT, 449 .flags = CLK_SET_RATE_PARENT, 463 .flags = CLK_SET_RATE_PARENT, 477 .flags = CLK_SET_RATE_PARENT, 519 .flags = CLK_SET_RATE_PARENT, 533 .flags = CLK_SET_RATE_PARENT, 547 .flags = CLK_SET_RATE_PARENT, 561 .flags = CLK_SET_RATE_PARENT, 575 .flags = CLK_SET_RATE_PARENT, 589 .flags = CLK_SET_RATE_PARENT, [all …]
|
H A D | dispcc-x1e80100.c | 263 .flags = CLK_SET_RATE_PARENT, 283 .flags = CLK_SET_RATE_PARENT, 298 .flags = CLK_SET_RATE_PARENT, 313 .flags = CLK_SET_RATE_PARENT, 328 .flags = CLK_SET_RATE_PARENT, 343 .flags = CLK_SET_RATE_PARENT, 358 .flags = CLK_SET_RATE_PARENT, 373 .flags = CLK_SET_RATE_PARENT, 388 .flags = CLK_SET_RATE_PARENT, 403 .flags = CLK_SET_RATE_PARENT, [all …]
|
H A D | dispcc1-sa8775p.c | 232 .flags = CLK_SET_RATE_PARENT, 252 .flags = CLK_SET_RATE_PARENT, 267 .flags = CLK_SET_RATE_PARENT, 282 .flags = CLK_SET_RATE_PARENT, 297 .flags = CLK_SET_RATE_PARENT, 312 .flags = CLK_SET_RATE_PARENT, 327 .flags = CLK_SET_RATE_PARENT, 342 .flags = CLK_SET_RATE_PARENT, 357 .flags = CLK_SET_RATE_PARENT, 372 .flags = CLK_SET_RATE_PARENT, [all …]
|
H A D | dispcc0-sa8775p.c | 232 .flags = CLK_SET_RATE_PARENT, 252 .flags = CLK_SET_RATE_PARENT, 267 .flags = CLK_SET_RATE_PARENT, 282 .flags = CLK_SET_RATE_PARENT, 297 .flags = CLK_SET_RATE_PARENT, 312 .flags = CLK_SET_RATE_PARENT, 327 .flags = CLK_SET_RATE_PARENT, 342 .flags = CLK_SET_RATE_PARENT, 357 .flags = CLK_SET_RATE_PARENT, 372 .flags = CLK_SET_RATE_PARENT, [all …]
|
H A D | camcc-sm8450.c | 113 .flags = CLK_SET_RATE_PARENT, 130 .flags = CLK_SET_RATE_PARENT, 146 .flags = CLK_SET_RATE_PARENT, 163 .flags = CLK_SET_RATE_PARENT, 218 .flags = CLK_SET_RATE_PARENT, 235 .flags = CLK_SET_RATE_PARENT, 323 .flags = CLK_SET_RATE_PARENT, 340 .flags = CLK_SET_RATE_PARENT, 395 .flags = CLK_SET_RATE_PARENT, 412 .flags = CLK_SET_RATE_PARENT, [all …]
|
H A D | camcc-sm8550.c | 110 .flags = CLK_SET_RATE_PARENT, 133 .flags = CLK_SET_RATE_PARENT, 187 .flags = CLK_SET_RATE_PARENT, 268 .flags = CLK_SET_RATE_PARENT, 322 .flags = CLK_SET_RATE_PARENT, 376 .flags = CLK_SET_RATE_PARENT, 430 .flags = CLK_SET_RATE_PARENT, 484 .flags = CLK_SET_RATE_PARENT, 538 .flags = CLK_SET_RATE_PARENT, 592 .flags = CLK_SET_RATE_PARENT, [all …]
|