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Searched refs:CLK_SCLK_SPI0 (Results 1 – 15 of 15) sorted by relevance

/linux/arch/arm/boot/dts/samsung/
H A Dexynos3250-artik5-eval.dts50 <&cmu CLK_DIV_SPI0_PRE>, <&cmu CLK_SCLK_SPI0>;
54 <&cmu CLK_DIV_SPI0_PRE>; /* for: CLK_SCLK_SPI0 */
H A Dexynos3250.dtsi824 clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>;
H A Dexynos4.dtsi620 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
H A Dexynos5420.dtsi659 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
/linux/include/dt-bindings/clock/
H A Dexynos5250.h51 #define CLK_SCLK_SPI0 154 macro
H A Dexynos7-clk.h41 #define CLK_SCLK_SPI0 7 macro
H A Dexynos4.h72 #define CLK_SCLK_SPI0 159 macro
H A Dexynos5420.h36 #define CLK_SCLK_SPI0 135 macro
H A Dexynos3250.h253 #define CLK_SCLK_SPI0 245 macro
H A Dexynos5433.h428 #define CLK_SCLK_SPI0 33 macro
/linux/drivers/clk/samsung/
H A Dclk-exynos5250.c511 GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi_pre0",
H A Dclk-exynos3250.c562 GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi0_pre",
H A Dclk-exynos5420.c990 GATE(CLK_SCLK_SPI0, "sclk_spi0", "dout_spi0_pre",
H A Dclk-exynos4.c792 GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi_pre0", SRC_MASK_PERIL1, 16,
H A Dclk-exynos5433.c1735 GATE(CLK_SCLK_SPI0, "sclk_spi0", "sclk_spi0_peric", ENABLE_SCLK_PERIC,