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Searched refs:CLK_MOUT_VPLLSRC (Results 1 – 6 of 6) sorted by relevance

/linux/include/dt-bindings/clock/
H A Dexynos5250.h178 #define CLK_MOUT_VPLLSRC 1030 macro
H A Dexynos4.h212 #define CLK_MOUT_VPLLSRC 398 macro
H A Dexynos3250.h52 #define CLK_MOUT_VPLLSRC 34 macro
/linux/drivers/clk/samsung/
H A Dclk-exynos5250.c104 #define CLKS_NR (CLK_MOUT_VPLLSRC + 1)
245 MUX(CLK_MOUT_VPLLSRC, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP2, 0, 1),
818 if (clk_hw_get_rate(hws[CLK_MOUT_VPLLSRC]) == 24 * MHZ) in exynos5250_clk_init()
H A Dclk-exynos4.c444 MUX(CLK_MOUT_VPLLSRC, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP1, 0, 1),
1305 if (clk_hw_get_rate(hws[CLK_MOUT_VPLLSRC]) == 24000000) in exynos4_clk_init()
H A Dclk-exynos3250.c280 MUX(CLK_MOUT_VPLLSRC, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP1, 0, 1),