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Searched refs:CLK_MM_MM_MDP_RSZ1 (Results 1 – 2 of 2) sorted by relevance

/linux/drivers/clk/mediatek/
H A Dclk-mt8365-mm.c39 GATE_MM0(CLK_MM_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_sel", 3),
/linux/include/dt-bindings/clock/
H A Dmediatek,mt8365-clk.h308 #define CLK_MM_MM_MDP_RSZ1 3 macro