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Searched refs:CLK_MM_MDP_TDSHP0 (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/clk/mediatek/
H A Dclk-mt6765-mm.c30 GATE_MM(CLK_MM_MDP_TDSHP0, "mm_mdp_tdshp0", "mm_ck", 4),
H A Dclk-mt6795-mm.c41 GATE_MM0(CLK_MM_MDP_TDSHP0, "mm_mdp_tdshp0", "mm_sel", 8),
H A Dclk-mt8173-mm.c45 GATE_MM0(CLK_MM_MDP_TDSHP0, "mm_mdp_tdshp0", "mm_sel", 8),
H A Dclk-mt2712-mm.c52 GATE_MM0(CLK_MM_MDP_TDSHP0, "mm_mdp_tdshp0", "mm_sel", 8),
/linux/include/dt-bindings/clock/
H A Dmediatek,mt6795-clk.h227 #define CLK_MM_MDP_TDSHP0 8 macro
H A Dmt8173-clk.h256 #define CLK_MM_MDP_TDSHP0 9 macro
H A Dmt6765-clk.h255 #define CLK_MM_MDP_TDSHP0 4 macro
H A Dmt2712-clk.h309 #define CLK_MM_MDP_TDSHP0 8 macro