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Searched refs:CLK_MM_DISP_SPLIT0 (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/clk/mediatek/
H A Dclk-mt6795-mm.c61 GATE_MM0(CLK_MM_DISP_SPLIT0, "mm_disp_split0", "mm_sel", 28),
H A Dclk-mt8173-mm.c64 GATE_MM0(CLK_MM_DISP_SPLIT0, "mm_disp_split0", "mm_sel", 28),
H A Dclk-mt2712-mm.c72 GATE_MM0(CLK_MM_DISP_SPLIT0, "mm_disp_split0", "mm_sel", 28),
/linux/include/dt-bindings/clock/
H A Dmediatek,mt6795-clk.h247 #define CLK_MM_DISP_SPLIT0 28 macro
H A Dmt8173-clk.h275 #define CLK_MM_DISP_SPLIT0 28 macro
H A Dmt2712-clk.h329 #define CLK_MM_DISP_SPLIT0 28 macro
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt6795.dtsi849 clocks = <&mmsys CLK_MM_DISP_SPLIT0>;
H A Dmt8173.dtsi1191 clocks = <&mmsys CLK_MM_DISP_SPLIT0>;