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Searched refs:CLK_MDP1_MDP_DLO_ASYNC2 (Results 1 – 2 of 2) sorted by relevance

/linux/drivers/clk/mediatek/
H A Dclk-mt8196-mdpsys.c90 GATE_MDP0(CLK_MDP1_MDP_DLO_ASYNC2, "mdp1_mdp_dlo_async2", "mdp", 23),
/linux/include/dt-bindings/clock/
H A Dmediatek,mt8196-clock.h757 #define CLK_MDP1_MDP_DLO_ASYNC2 24 macro