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Searched refs:CLK_MCU_BUS_DIV_SEL (Results 1 – 2 of 2) sorted by relevance

/linux/include/dt-bindings/clock/
H A Dmediatek,mt7988-clk.h136 #define CLK_MCU_BUS_DIV_SEL 0 macro
/linux/drivers/clk/mediatek/
H A Dclk-mt7988-topckgen.c297 MUX_GATE_FLAGS(CLK_MCU_BUS_DIV_SEL, "mcu_bus_div_sel", mcu_bus_div_parents, 0x7C0, 9, 2, -1,