Searched refs:CLK_LSE (Results 1 – 5 of 5) sorted by relevance
25 #define CLK_LSE 3 macro
77 3 CLK_LSE (generated from a 32.768 kHz low-speed external
1840 clks[CLK_LSE] = clk_register_rgate(NULL, "lse", "clk-lse", 0, in stm32f4_rcc_init()1843 if (IS_ERR(clks[CLK_LSE])) { in stm32f4_rcc_init()
253 assigned-clock-parents = <&rcc 1 CLK_LSE>;
271 assigned-clock-parents = <&rcc 1 CLK_LSE>;