Searched refs:CLK_GOUT_FSYS0_PCIE_GEN3_4L_X2_SLV_ACLK (Results 1 – 2 of 2) sorted by relevance
226 #define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X2_SLV_ACLK 30 macro
1362 GATE(CLK_GOUT_FSYS0_PCIE_GEN3_4L_X2_SLV_ACLK,