Searched refs:CLK_FIN_PLL (Results 1 – 14 of 14) sorted by relevance
13 #define CLK_FIN_PLL 1 macro
15 #define CLK_FIN_PLL 3 macro
26 #define CLK_FIN_PLL 2 macro
352 clocks = <&cmu CLK_FIN_PLL>;402 assigned-clock-parents = <&cmu CLK_FIN_PLL>,403 <&cmu CLK_FIN_PLL>;455 clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
295 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>,927 clocks = <&clock CLK_FIN_PLL>;1291 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
286 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
299 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
672 assigned-clock-parents = <&clock CLK_FIN_PLL>;
946 assigned-clock-parents = <&clock CLK_FIN_PLL>;
928 assigned-clock-parents = <&clock CLK_FIN_PLL>;
70 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
1059 fclk.id = CLK_FIN_PLL; in exynos4_clk_register_finpll()1337 if (clk_hw_get_rate(hws[CLK_FIN_PLL]) == 24000000) { in exynos4_clk_init()1351 if (clk_hw_get_rate(hws[CLK_FIN_PLL]) == 24000000) { in exynos4_clk_init()