Searched refs:CLK_DIV_8 (Results 1 – 5 of 5) sorted by relevance
606 while ((n < MIN_DIV_N_PCR - 4) && (div < CLK_DIV_8)) { in rts5228_pci_switch_clock()636 } else if (div == CLK_DIV_8) { in rts5228_pci_switch_clock()
685 while ((n < MIN_DIV_N_PCR - 4) && (div < CLK_DIV_8)) { in rts5261_pci_switch_clock()715 } else if (div == CLK_DIV_8) { in rts5261_pci_switch_clock()
829 while ((n < MIN_DIV_N_PCR - 4) && (div < CLK_DIV_8)) { in rts5264_pci_switch_clock()859 } else if (div == CLK_DIV_8) { in rts5264_pci_switch_clock()
748 while ((n < MIN_DIV_N_PCR) && (div < CLK_DIV_8)) { in rtsx_pci_switch_clock()
458 #define CLK_DIV_8 0x04 macro