| /linux/include/dt-bindings/clock/ |
| H A D | mediatek,mt6735-apmixedsys.h | 6 #define CLK_APMIXED_ARMPLL 0 macro
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| H A D | mt7986-clk.h | 12 #define CLK_APMIXED_ARMPLL 0 macro
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| H A D | mt7629-clk.h | 155 #define CLK_APMIXED_ARMPLL 0 macro
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| H A D | mediatek,mt7981-clk.h | 188 #define CLK_APMIXED_ARMPLL 0 macro
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| H A D | mt8516-clk.h | 13 #define CLK_APMIXED_ARMPLL 0 macro
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| H A D | mt7622-clk.h | 170 #define CLK_APMIXED_ARMPLL 0 macro
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| H A D | mt6765-clk.h | 11 #define CLK_APMIXED_ARMPLL 1 macro
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| H A D | mediatek,mt8365-clk.h | 231 #define CLK_APMIXED_ARMPLL 0 macro
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| H A D | mt2701-clk.h | 175 #define CLK_APMIXED_ARMPLL 1 macro
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| /linux/drivers/clk/mediatek/ |
| H A D | clk-mt7981-apmixed.c | 45 PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x00000001, PLL_AO,
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| H A D | clk-mt7986-apmixed.c | 43 PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x0, PLL_AO, 32,
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| H A D | clk-mt8516-apmixedsys.c | 60 PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0100, 0x0110, 0, 0,
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| H A D | clk-mt8167-apmixedsys.c | 59 PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0100, 0x0110, 0, 0,
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| H A D | clk-mt7629.c | 313 PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0,
643 clk_prepare_enable(clk_data->hws[CLK_APMIXED_ARMPLL]->clk); in mtk_apmixedsys_init()
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| H A D | clk-mt7622-apmixedsys.c | 59 PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0,
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| H A D | clk-mt6735-apmixedsys.c | 69 …PLL(CLK_APMIXED_ARMPLL, "armpll", ARMPLL_CON0, ARMPLL_PWR_CON0, 0x00000001, 0, ARMPLL_CON1, 24, 0,…
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| H A D | clk-mt8365-apmixedsys.c | 83 PLL_B(CLK_APMIXED_ARMPLL, "armpll", 0x030C, 0x0318, 0x00000001, PLL_AO,
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| H A D | clk-mt6765.c | 707 PLL(CLK_APMIXED_ARMPLL, "armpll", 0x020C, 0x0218, 0,
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| H A D | clk-mt2701.c | 940 PLL(CLK_APMIXED_ARMPLL, "armpll", 0x200, 0x20c, 0x80000000,
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