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Searched refs:CLKID_VCLK_DIV1 (Results 1 – 10 of 10) sorted by relevance

/linux/include/dt-bindings/clock/
H A Daxg-clkc.h132 #define CLKID_VCLK_DIV1 122 macro
H A Dgxbb-clkc.h193 #define CLKID_VCLK_DIV1 185 macro
H A Dmeson8b-clkc.h147 #define CLKID_VCLK_DIV1 140 macro
H A Damlogic,s4-peripherals-clkc.h49 #define CLKID_VCLK_DIV1 39 macro
H A Dg12a-clkc.h159 #define CLKID_VCLK_DIV1 148 macro
/linux/drivers/clk/meson/
H A Dmeson8b.c2912 [CLKID_VCLK_DIV1] = &meson8b_vclk_div1_gate.hw,
3116 [CLKID_VCLK_DIV1] = &meson8b_vclk_div1_gate.hw,
3331 [CLKID_VCLK_DIV1] = &meson8b_vclk_div1_gate.hw,
H A Dgxbb.c2904 [CLKID_VCLK_DIV1] = &gxbb_vclk_div1.hw,
3111 [CLKID_VCLK_DIV1] = &gxbb_vclk_div1.hw,
H A Dg12a.c4515 [CLKID_VCLK_DIV1] = &g12a_vclk_div1.hw,
4742 [CLKID_VCLK_DIV1] = &g12a_vclk_div1.hw,
5010 [CLKID_VCLK_DIV1] = &g12a_vclk_div1.hw,
H A Daxg.c2011 [CLKID_VCLK_DIV1] = &axg_vclk_div1.hw,
H A Ds4-peripherals.c3338 [CLKID_VCLK_DIV1] = &s4_vclk_div1.hw,