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Searched refs:CLKID_MPLL1_DIV (Results 1 – 8 of 8) sorted by relevance

/linux/include/dt-bindings/clock/
H A Damlogic,s4-pll-clkc.h36 #define CLKID_MPLL1_DIV 26 macro
H A Daxg-clkc.h77 #define CLKID_MPLL1_DIV 66 macro
H A Dgxbb-clkc.h151 #define CLKID_MPLL1_DIV 143 macro
H A Dmeson8b-clkc.h104 #define CLKID_MPLL1_DIV 97 macro
H A Dg12a-clkc.h81 #define CLKID_MPLL1_DIV 70 macro
/linux/drivers/clk/meson/
H A Ds4-pll.c789 [CLKID_MPLL1_DIV] = &s4_mpll1_div.hw,
H A Dmeson8b.c2907 [CLKID_MPLL1_DIV] = &meson8b_mpll1_div.hw,
3111 [CLKID_MPLL1_DIV] = &meson8b_mpll1_div.hw,
3326 [CLKID_MPLL1_DIV] = &meson8b_mpll1_div.hw,
H A Daxg.c2053 [CLKID_MPLL1_DIV] = &axg_mpll1_div.hw,