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Searched refs:CLKID_MPLL0_DIV (Results 1 – 8 of 8) sorted by relevance

/linux/include/dt-bindings/clock/
H A Damlogic,s4-pll-clkc.h34 #define CLKID_MPLL0_DIV 24 macro
H A Daxg-clkc.h76 #define CLKID_MPLL0_DIV 65 macro
H A Dgxbb-clkc.h150 #define CLKID_MPLL0_DIV 142 macro
H A Dmeson8b-clkc.h103 #define CLKID_MPLL0_DIV 96 macro
H A Dg12a-clkc.h80 #define CLKID_MPLL0_DIV 69 macro
/linux/drivers/clk/meson/
H A Ds4-pll.c787 [CLKID_MPLL0_DIV] = &s4_mpll0_div.hw,
H A Dmeson8b.c2906 [CLKID_MPLL0_DIV] = &meson8b_mpll0_div.hw,
3110 [CLKID_MPLL0_DIV] = &meson8b_mpll0_div.hw,
3325 [CLKID_MPLL0_DIV] = &meson8b_mpll0_div.hw,
H A Daxg.c2052 [CLKID_MPLL0_DIV] = &axg_mpll0_div.hw,