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Searched refs:CLKID_MPLL0_DIV (Results 1 – 10 of 10) sorted by relevance

/linux/include/dt-bindings/clock/
H A Damlogic,s4-pll-clkc.h34 #define CLKID_MPLL0_DIV 24 macro
H A Daxg-clkc.h76 #define CLKID_MPLL0_DIV 65 macro
H A Dgxbb-clkc.h150 #define CLKID_MPLL0_DIV 142 macro
H A Dmeson8b-clkc.h103 #define CLKID_MPLL0_DIV 96 macro
H A Dg12a-clkc.h80 #define CLKID_MPLL0_DIV 69 macro
/linux/drivers/clk/meson/
H A Ds4-pll.c760 [CLKID_MPLL0_DIV] = &s4_mpll0_div.hw,
H A Dmeson8b.c2867 [CLKID_MPLL0_DIV] = &meson8b_mpll0_div.hw,
3071 [CLKID_MPLL0_DIV] = &meson8b_mpll0_div.hw,
3286 [CLKID_MPLL0_DIV] = &meson8b_mpll0_div.hw,
H A Dgxbb.c2869 [CLKID_MPLL0_DIV] = &gxbb_mpll0_div.hw,
3076 [CLKID_MPLL0_DIV] = &gxl_mpll0_div.hw,
H A Dg12a.c4445 [CLKID_MPLL0_DIV] = &g12a_mpll0_div.hw,
4672 [CLKID_MPLL0_DIV] = &g12a_mpll0_div.hw,
4940 [CLKID_MPLL0_DIV] = &g12a_mpll0_div.hw,
H A Daxg.c1955 [CLKID_MPLL0_DIV] = &axg_mpll0_div.hw,