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Searched refs:CCI_REG32 (Results 1 – 6 of 6) sorted by relevance

/linux/drivers/media/i2c/ccs/
H A Dsmiapp-reg-defs.h37 #define SMIAPP_REG_U32_SERIAL_NUMBER CCI_REG32(0x001c)
41 #define SMIAPP_REG_U32_FRAME_FORMAT_DESCRIPTOR_4(n) CCI_REG32(0x0060 + ((n) << 2)) /* 0 <= n <= 7 …
142 #define SMIAPP_REG_U32_REQUESTED_LINK_BIT_RATE_MBPS CCI_REG32(0x0820)
378 #define SMIAPP_REG_F32_MIN_EXT_CLK_FREQ_HZ (CCI_REG32(0x1100) | CCS_FL_FLOAT_IREAL)
379 #define SMIAPP_REG_F32_MAX_EXT_CLK_FREQ_HZ (CCI_REG32(0x1104) | CCS_FL_FLOAT_IREAL)
382 #define SMIAPP_REG_F32_MIN_PLL_IP_FREQ_HZ (CCI_REG32(0x110c) | CCS_FL_FLOAT_IREAL)
383 #define SMIAPP_REG_F32_MAX_PLL_IP_FREQ_HZ (CCI_REG32(0x1110) | CCS_FL_FLOAT_IREAL)
386 #define SMIAPP_REG_F32_MIN_PLL_OP_FREQ_HZ (CCI_REG32(0x1118) | CCS_FL_FLOAT_IREAL)
387 #define SMIAPP_REG_F32_MAX_PLL_OP_FREQ_HZ (CCI_REG32(0x111c) | CCS_FL_FLOAT_IREAL)
390 #define SMIAPP_REG_F32_MIN_VT_SYS_CLK_FREQ_HZ (CCI_REG32(0x1124) | CCS_FL_FLOAT_IREAL)
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H A Dccs-regs.h51 #define CCS_R_SERIAL_NUMBER CCI_REG32(0x001c)
65 #define CCS_R_FRAME_FORMAT_DESCRIPTOR_4(n) CCI_REG32(0x0060 + (n) * 4)
284 #define CCS_R_REQUESTED_LINK_RATE CCI_REG32(0x0820)
480 #define CCS_R_ADC_BIT_DEPTH_CAPABILITY CCI_REG32(0x10f4)
481 #define CCS_R_MIN_EXT_CLK_FREQ_MHZ (CCI_REG32(0x1100) | CCS_FL_FLOAT_IREAL)
482 #define CCS_R_MAX_EXT_CLK_FREQ_MHZ (CCI_REG32(0x1104) | CCS_FL_FLOAT_IREAL)
485 #define CCS_R_MIN_PLL_IP_CLK_FREQ_MHZ (CCI_REG32(0x110c) | CCS_FL_FLOAT_IREAL)
486 #define CCS_R_MAX_PLL_IP_CLK_FREQ_MHZ (CCI_REG32(0x1110) | CCS_FL_FLOAT_IREAL)
489 #define CCS_R_MIN_PLL_OP_CLK_FREQ_MHZ (CCI_REG32(0x1118) | CCS_FL_FLOAT_IREAL)
490 #define CCS_R_MAX_PLL_OP_CLK_FREQ_MHZ (CCI_REG32(0x111c) | CCS_FL_FLOAT_IREAL)
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/linux/include/media/
H A Dv4l2-cci.h51 #define CCI_REG32(x) ((4 << CCI_REG_WIDTH_SHIFT) | (x)) macro
/linux/drivers/media/i2c/
H A Dalvium-csi2.h25 #define REG_BCRM_V4L2_32BIT(n) (REG_BCRM_V4L2 | CCI_REG32(n))
H A Dthp7312.c109 #define THP7312_REG_FW_DRIVABILITY CCI_REG32(0xd65c)
110 #define THP7312_REG_FW_DEST_BANK_ADDR CCI_REG32(0xff08)
116 #define THP7312_REG_FW_CRC_RESULT CCI_REG32(0xff64)
H A Dmt9m114.c90 #define MT9M114_CAM_SENSOR_CFG_PIXCLK CCI_REG32(0xc808)
296 #define MT9M114_PATCHLDR_FIRMWARE_ID CCI_REG32(0xe004)