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/linux/arch/sh/kernel/cpu/sh4a/
H A Dperf_event.c109 #define C(x) PERF_COUNT_HW_CACHE_##x macro
116 [ C(L1D) ] = {
117 [ C(OP_READ) ] = {
118 [ C(RESULT_ACCESS) ] = 0x0031,
119 [ C(RESULT_MISS) ] = 0x0032,
121 [ C(OP_WRITE) ] = {
122 [ C(RESULT_ACCESS) ] = 0x0039,
123 [ C(RESULT_MISS) ] = 0x003a,
125 [ C(OP_PREFETCH) ] = {
126 [ C(RESULT_ACCESS) ] = 0,
[all …]
/linux/arch/sh/kernel/cpu/sh4/
H A Dperf_event.c84 #define C(x) PERF_COUNT_HW_CACHE_##x macro
91 [ C(L1D) ] = {
92 [ C(OP_READ) ] = {
93 [ C(RESULT_ACCESS) ] = 0x0001,
94 [ C(RESULT_MISS) ] = 0x0004,
96 [ C(OP_WRITE) ] = {
97 [ C(RESULT_ACCESS) ] = 0x0002,
98 [ C(RESULT_MISS) ] = 0x0005,
100 [ C(OP_PREFETCH) ] = {
101 [ C(RESULT_ACCESS) ] = 0,
[all …]
/linux/arch/powerpc/perf/
H A Dpower10-pmu.c351 #define C(x) PERF_COUNT_HW_CACHE_##x macro
358 static u64 power10_cache_events_dd1[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
359 [C(L1D)] = {
360 [C(OP_READ)] = {
361 [C(RESULT_ACCESS)] = PM_LD_REF_L1,
362 [C(RESULT_MISS)] = PM_LD_MISS_L1,
364 [C(OP_WRITE)] = {
365 [C(RESULT_ACCESS)] = 0,
366 [C(RESULT_MISS)] = PM_ST_MISS_L1,
368 [C(OP_PREFETCH)] = {
[all …]
H A Dgeneric-compat-pmu.c178 #define C(x) PERF_COUNT_HW_CACHE_##x macro
185 static u64 generic_compat_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
186 [ C(L1D) ] = {
187 [ C(OP_READ) ] = {
188 [ C(RESULT_ACCESS) ] = 0,
189 [ C(RESULT_MISS) ] = PM_LD_MISS_L1,
191 [ C(OP_WRITE) ] = {
192 [ C(RESULT_ACCESS) ] = 0,
193 [ C(RESULT_MISS) ] = PM_ST_MISS_L1,
195 [ C(OP_PREFETCH) ] = {
[all …]
H A Dpower8-pmu.c259 #define C(x) PERF_COUNT_HW_CACHE_##x macro
266 static u64 power8_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
267 [ C(L1D) ] = {
268 [ C(OP_READ) ] = {
269 [ C(RESULT_ACCESS) ] = PM_LD_REF_L1,
270 [ C(RESULT_MISS) ] = PM_LD_MISS_L1,
272 [ C(OP_WRITE) ] = {
273 [ C(RESULT_ACCESS) ] = 0,
274 [ C(RESULT_MISS) ] = PM_ST_MISS_L1,
276 [ C(OP_PREFETCH) ] = {
[all …]
H A Dpower9-pmu.c330 #define C(x) PERF_COUNT_HW_CACHE_##x macro
337 static u64 power9_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
338 [ C(L1D) ] = {
339 [ C(OP_READ) ] = {
340 [ C(RESULT_ACCESS) ] = PM_LD_REF_L1,
341 [ C(RESULT_MISS) ] = PM_LD_MISS_L1_FIN,
343 [ C(OP_WRITE) ] = {
344 [ C(RESULT_ACCESS) ] = 0,
345 [ C(RESULT_MISS) ] = PM_ST_MISS_L1,
347 [ C(OP_PREFETCH) ] = {
[all …]
H A De6500-pmu.c28 #define C(x) PERF_COUNT_HW_CACHE_##x macro
35 static int e6500_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
36 [C(L1D)] = {
38 [C(OP_READ)] = { 27, 222 },
39 [C(OP_WRITE)] = { 28, 223 },
40 [C(OP_PREFETCH)] = { 29, 0 },
42 [C(L1I)] = {
44 [C(OP_READ)] = { 2, 254 },
45 [C(OP_WRITE)] = { -1, -1 },
46 [C(OP_PREFETCH)] = { 37, 0 },
[all …]
H A De500-pmu.c27 #define C(x) PERF_COUNT_HW_CACHE_##x macro
34 static int e500_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
39 [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */
40 [C(OP_READ)] = { 27, 0 },
41 [C(OP_WRITE)] = { 28, 0 },
42 [C(OP_PREFETCH)] = { 29, 0 },
44 [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */
45 [C(OP_READ)] = { 2, 60 },
46 [C(OP_WRITE)] = { -1, -1 },
47 [C(OP_PREFETCH)] = { 0, 0 },
[all …]
H A Dmpc7450-pmu.c358 #define C(x) PERF_COUNT_HW_CACHE_##x macro
365 static u64 mpc7450_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
366 [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */
367 [C(OP_READ)] = { 0, 0x225 },
368 [C(OP_WRITE)] = { 0, 0x227 },
369 [C(OP_PREFETCH)] = { 0, 0 },
371 [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */
372 [C(OP_READ)] = { 0x129, 0x115 },
373 [C(OP_WRITE)] = { -1, -1 },
374 [C(OP_PREFETCH)] = { 0x634, 0 },
[all …]
H A Dpower7-pmu.c332 #define C(x) PERF_COUNT_HW_CACHE_##x macro
339 static u64 power7_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
340 [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */
341 [C(OP_READ)] = { 0xc880, 0x400f0 },
342 [C(OP_WRITE)] = { 0, 0x300f0 },
343 [C(OP_PREFETCH)] = { 0xd8b8, 0 },
345 [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */
346 [C(OP_READ)] = { 0, 0x200fc },
347 [C(OP_WRITE)] = { -1, -1 },
348 [C(OP_PREFETCH)] = { 0x408a, 0 },
[all …]
H A Dppc970-pmu.c431 #define C(x) PERF_COUNT_HW_CACHE_##x macro
438 static u64 ppc970_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
439 [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */
440 [C(OP_READ)] = { 0x8810, 0x3810 },
441 [C(OP_WRITE)] = { 0x7810, 0x813 },
442 [C(OP_PREFETCH)] = { 0x731, 0 },
444 [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */
445 [C(OP_READ)] = { 0, 0 },
446 [C(OP_WRITE)] = { -1, -1 },
447 [C(OP_PREFETCH)] = { 0, 0 },
[all …]
H A Dpower6-pmu.c491 #define C(x) PERF_COUNT_HW_CACHE_##x macro
499 static u64 power6_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
500 [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */
501 [C(OP_READ)] = { 0x280030, 0x80080 },
502 [C(OP_WRITE)] = { 0x180032, 0x80088 },
503 [C(OP_PREFETCH)] = { 0x810a4, 0 },
505 [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */
506 [C(OP_READ)] = { 0, 0x100056 },
507 [C(OP_WRITE)] = { -1, -1 },
508 [C(OP_PREFETCH)] = { 0x4008c, 0 },
[all …]
H A Dpower5-pmu.c560 #define C(x) PERF_COUNT_HW_CACHE_##x macro
567 static u64 power5_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
568 [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */
569 [C(OP_READ)] = { 0x4c1090, 0x3c1088 },
570 [C(OP_WRITE)] = { 0x3c1090, 0xc10c3 },
571 [C(OP_PREFETCH)] = { 0xc70e7, 0 },
573 [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */
574 [C(OP_READ)] = { 0, 0 },
575 [C(OP_WRITE)] = { -1, -1 },
576 [C(OP_PREFETCH)] = { 0, 0 },
[all …]
/linux/arch/sparc/kernel/
H A Dperf_event.c147 #define C(x) PERF_COUNT_HW_CACHE_##x macro
221 [C(L1D)] = {
222 [C(OP_READ)] = {
223 [C(RESULT_ACCESS)] = { 0x09, PIC_LOWER, },
224 [C(RESULT_MISS)] = { 0x09, PIC_UPPER, },
226 [C(OP_WRITE)] = {
227 [C(RESULT_ACCESS)] = { 0x0a, PIC_LOWER },
228 [C(RESULT_MISS)] = { 0x0a, PIC_UPPER },
230 [C(OP_PREFETCH)] = {
231 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
[all …]
/linux/tools/testing/selftests/bpf/progs/
H A Dtest_verif_scale2.c20 #define C do { \ in balancer_ingress() macro
26 #define C30 C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C; in balancer_ingress()
H A Dtest_verif_scale1.c20 #define C do { \ in balancer_ingress() macro
26 #define C30 C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C; in balancer_ingress()
H A Dtest_verif_scale3.c20 #define C do { \ in balancer_ingress() macro
26 #define C30 C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C; in balancer_ingress()
H A Dcore_kern.c85 #define C do { \ in balancer_ingress() macro
99 #define C30 C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C; in balancer_ingress()
/linux/arch/x86/events/intel/
H A Dcore.c635 [ C(L1D ) ] = {
636 [ C(OP_READ) ] = {
637 [ C(RESULT_ACCESS) ] = 0x81d0,
638 [ C(RESULT_MISS) ] = 0xe124,
640 [ C(OP_WRITE) ] = {
641 [ C(RESULT_ACCESS) ] = 0x82d0,
644 [ C(L1I ) ] = {
645 [ C(OP_READ) ] = {
646 [ C(RESULT_MISS) ] = 0xe424,
648 [ C(OP_WRITE) ] = {
[all …]
/linux/drivers/perf/
H A Driscv_pmu_sbi.c157 #define C(x) PERF_COUNT_HW_CACHE_##x macro
161 [C(L1D)] = {
162 [C(OP_READ)] = {
163 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
164 C(OP_READ), C(L1D), SBI_PMU_EVENT_TYPE_CACHE, 0}},
165 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
166 C(OP_READ), C(L1D), SBI_PMU_EVENT_TYPE_CACHE, 0}},
168 [C(OP_WRITE)] = {
169 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
170 C(OP_WRITE), C(L1D), SBI_PMU_EVENT_TYPE_CACHE, 0}},
[all …]
/linux/kernel/trace/
H A Dtrace_probe.h486 C(FILE_NOT_FOUND, "Failed to find the given file"), \
487 C(NO_REGULAR_FILE, "Not a regular file"), \
488 C(BAD_REFCNT, "Invalid reference counter offset"), \
489 C(REFCNT_OPEN_BRACE, "Reference counter brace is not closed"), \
490 C(BAD_REFCNT_SUFFIX, "Reference counter has wrong suffix"), \
491 C(BAD_UPROBE_OFFS, "Invalid uprobe offset"), \
492 C(BAD_MAXACT_TYPE, "Maxactive is only for function exit"), \
493 C(BAD_MAXACT, "Invalid maxactive number"), \
494 C(MAXACT_TOO_BIG, "Maxactive is too big"), \
495 C(BAD_PROBE_ADDR, "Invalid probed address or symbol"), \
[all …]
/linux/lib/zstd/common/
H A Dcpu.h98 #define C(name, bit) X(name, f1c, bit) macro
99 C(sse3, 0)
100 C(pclmuldq, 1)
101 C(dtes64, 2)
102 C(monitor, 3)
103 C(dscpl, 4)
104 C(vmx, 5)
105 C(smx, 6)
106 C(eist, 7)
107 C(tm2, 8)
[all …]
/linux/drivers/scsi/isci/
H A Drequest.h228 C(REQ_INIT),\
229 C(REQ_CONSTRUCTED),\
230 C(REQ_STARTED),\
231 C(REQ_STP_UDMA_WAIT_TC_COMP),\
232 C(REQ_STP_UDMA_WAIT_D2H),\
233 C(REQ_STP_NON_DATA_WAIT_H2D),\
234 C(REQ_STP_NON_DATA_WAIT_D2H),\
235 C(REQ_STP_PIO_WAIT_H2D),\
236 C(REQ_STP_PIO_WAIT_FRAME),\
237 C(REQ_STP_PIO_DATA_IN),\
[all …]
H A Dphy.h377 C(PHY_INITIAL),\
378 C(PHY_STOPPED),\
379 C(PHY_STARTING),\
380 C(PHY_SUB_INITIAL),\
381 C(PHY_SUB_AWAIT_OSSP_EN),\
382 C(PHY_SUB_AWAIT_SAS_SPEED_EN),\
383 C(PHY_SUB_AWAIT_IAF_UF),\
384 C(PHY_SUB_AWAIT_SAS_POWER),\
385 C(PHY_SUB_AWAIT_SATA_POWER),\
386 C(PHY_SUB_AWAIT_SATA_PHY_EN),\
[all …]
H A Dremote_device.h238 C(DEV_INITIAL),\
239 C(DEV_STOPPED),\
240 C(DEV_STARTING),\
241 C(DEV_READY),\
242 C(STP_DEV_IDLE),\
243 C(STP_DEV_CMD),\
244 C(STP_DEV_NCQ),\
245 C(STP_DEV_NCQ_ERROR),\
246 C(STP_DEV_ATAPI_ERROR),\
247 C(STP_DEV_AWAIT_RESET),\
[all …]

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