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Searched refs:BIT_ULL (Results 1 – 25 of 403) sorted by relevance

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/linux/drivers/gpu/drm/panfrost/
H A Dpanfrost_issues.h142 BIT_ULL(HW_ISSUE_9435))
145 BIT_ULL(HW_ISSUE_6367) | \
146 BIT_ULL(HW_ISSUE_6787) | \
147 BIT_ULL(HW_ISSUE_8408) | \
148 BIT_ULL(HW_ISSUE_9510) | \
149 BIT_ULL(HW_ISSUE_10649) | \
150 BIT_ULL(HW_ISSUE_10676) | \
151 BIT_ULL(HW_ISSUE_10883) | \
152 BIT_ULL(HW_ISSUE_11020) | \
153 BIT_ULL(HW_ISSUE_11035) | \
[all …]
/linux/arch/mips/include/asm/
H A Dcpu.h359 #define MIPS_CPU_TLB BIT_ULL( 0) /* CPU has TLB */
360 #define MIPS_CPU_4KEX BIT_ULL( 1) /* "R4K" exception model */
361 #define MIPS_CPU_3K_CACHE BIT_ULL( 2) /* R3000-style caches */
362 #define MIPS_CPU_4K_CACHE BIT_ULL( 3) /* R4000-style caches */
363 #define MIPS_CPU_FPU BIT_ULL( 5) /* CPU has FPU */
364 #define MIPS_CPU_32FPR BIT_ULL( 6) /* 32 dbl. prec. FP registers */
365 #define MIPS_CPU_COUNTER BIT_ULL( 7) /* Cycle count/compare */
366 #define MIPS_CPU_WATCH BIT_ULL( 8) /* watchpoint registers */
367 #define MIPS_CPU_DIVEC BIT_ULL( 9) /* dedicated interrupt vector */
368 #define MIPS_CPU_VCE BIT_ULL(10) /* virt. coherence conflict possible */
[all …]
/linux/drivers/mmc/host/
H A Dcavium.h120 #define MIO_EMM_DMA_FIFO_CFG_CLR BIT_ULL(16)
124 #define MIO_EMM_DMA_FIFO_CMD_RW BIT_ULL(62)
125 #define MIO_EMM_DMA_FIFO_CMD_INTDIS BIT_ULL(60)
126 #define MIO_EMM_DMA_FIFO_CMD_SWAP32 BIT_ULL(59)
127 #define MIO_EMM_DMA_FIFO_CMD_SWAP16 BIT_ULL(58)
128 #define MIO_EMM_DMA_FIFO_CMD_SWAP8 BIT_ULL(57)
129 #define MIO_EMM_DMA_FIFO_CMD_ENDIAN BIT_ULL(56)
132 #define MIO_EMM_CMD_SKIP_BUSY BIT_ULL(62)
134 #define MIO_EMM_CMD_VAL BIT_ULL(59)
135 #define MIO_EMM_CMD_DBUF BIT_ULL(55)
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/linux/drivers/net/ethernet/cavium/thunder/
H A Dthunder_bgx.h36 #define CMR_PKT_TX_EN BIT_ULL(13)
37 #define CMR_PKT_RX_EN BIT_ULL(14)
38 #define CMR_EN BIT_ULL(15)
40 #define CMR_GLOBAL_CFG_FCS_STRIP BIT_ULL(6)
57 #define RX_DMACX_CAM_EN BIT_ULL(48)
87 #define SPU_CTL_LOW_POWER BIT_ULL(11)
88 #define SPU_CTL_LOOPBACK BIT_ULL(14)
89 #define SPU_CTL_RESET BIT_ULL(15)
91 #define SPU_STATUS1_RCV_LNK BIT_ULL(2)
93 #define SPU_STATUS2_RCVFLT BIT_ULL(10)
[all …]
/linux/drivers/ras/amd/atl/
H A Ddehash.c20 intlv_bit = !!(BIT_ULL(intlv_bit_pos) & ctx->ret_addr); in df2_dehash_addr()
23 hashed_bit ^= FIELD_GET(BIT_ULL(12), ctx->ret_addr); in df2_dehash_addr()
24 hashed_bit ^= FIELD_GET(BIT_ULL(18), ctx->ret_addr); in df2_dehash_addr()
25 hashed_bit ^= FIELD_GET(BIT_ULL(21), ctx->ret_addr); in df2_dehash_addr()
26 hashed_bit ^= FIELD_GET(BIT_ULL(30), ctx->ret_addr); in df2_dehash_addr()
29 ctx->ret_addr ^= BIT_ULL(intlv_bit_pos); in df2_dehash_addr()
44 intlv_bit = !!(BIT_ULL(intlv_bit_pos) & ctx->ret_addr); in df3_dehash_addr()
47 hashed_bit ^= FIELD_GET(BIT_ULL(14), ctx->ret_addr); in df3_dehash_addr()
48 hashed_bit ^= FIELD_GET(BIT_ULL(18), ctx->ret_addr) & hash_ctl_64k; in df3_dehash_addr()
49 hashed_bit ^= FIELD_GET(BIT_ULL(23), ctx->ret_addr) & hash_ctl_2M; in df3_dehash_addr()
[all …]
H A Ddenormalize.c463 hash_pa8 = FIELD_GET(BIT_ULL(8), denorm_ctx->current_spa); in get_logical_coh_st_fabric_id_for_current_spa()
464 hash_pa8 ^= FIELD_GET(BIT_ULL(14), denorm_ctx->current_spa); in get_logical_coh_st_fabric_id_for_current_spa()
465 hash_pa8 ^= FIELD_GET(BIT_ULL(16), denorm_ctx->current_spa) & hash_ctl_64k; in get_logical_coh_st_fabric_id_for_current_spa()
466 hash_pa8 ^= FIELD_GET(BIT_ULL(21), denorm_ctx->current_spa) & hash_ctl_2M; in get_logical_coh_st_fabric_id_for_current_spa()
467 hash_pa8 ^= FIELD_GET(BIT_ULL(30), denorm_ctx->current_spa) & hash_ctl_1G; in get_logical_coh_st_fabric_id_for_current_spa()
468 hash_pa8 ^= FIELD_GET(BIT_ULL(40), denorm_ctx->current_spa) & hash_ctl_1T; in get_logical_coh_st_fabric_id_for_current_spa()
470 hash_pa9 = FIELD_GET(BIT_ULL(9), denorm_ctx->current_spa); in get_logical_coh_st_fabric_id_for_current_spa()
471 hash_pa9 ^= FIELD_GET(BIT_ULL(17), denorm_ctx->current_spa) & hash_ctl_64k; in get_logical_coh_st_fabric_id_for_current_spa()
472 hash_pa9 ^= FIELD_GET(BIT_ULL(22), denorm_ctx->current_spa) & hash_ctl_2M; in get_logical_coh_st_fabric_id_for_current_spa()
473 hash_pa9 ^= FIELD_GET(BIT_ULL(31), denorm_ctx->current_spa) & hash_ctl_1G; in get_logical_coh_st_fabric_id_for_current_spa()
[all …]
/linux/arch/loongarch/include/asm/
H A Dcpu.h129 #define LOONGARCH_CPU_CPUCFG BIT_ULL(CPU_FEATURE_CPUCFG)
130 #define LOONGARCH_CPU_LAM BIT_ULL(CPU_FEATURE_LAM)
131 #define LOONGARCH_CPU_UAL BIT_ULL(CPU_FEATURE_UAL)
132 #define LOONGARCH_CPU_FPU BIT_ULL(CPU_FEATURE_FPU)
133 #define LOONGARCH_CPU_LSX BIT_ULL(CPU_FEATURE_LSX)
134 #define LOONGARCH_CPU_LASX BIT_ULL(CPU_FEATURE_LASX)
135 #define LOONGARCH_CPU_CRC32 BIT_ULL(CPU_FEATURE_CRC32)
136 #define LOONGARCH_CPU_COMPLEX BIT_ULL(CPU_FEATURE_COMPLEX)
137 #define LOONGARCH_CPU_CRYPTO BIT_ULL(CPU_FEATURE_CRYPTO)
138 #define LOONGARCH_CPU_LVZ BIT_ULL(CPU_FEATURE_LVZ)
[all …]
/linux/drivers/gpu/drm/xe/regs/
H A Dxe_gtt_defs.h9 #define XELPG_GGTT_PTE_PAT0 BIT_ULL(52)
10 #define XELPG_GGTT_PTE_PAT1 BIT_ULL(53)
16 #define XELPG_PPGTT_PTE_PAT3 BIT_ULL(62)
17 #define XE2_PPGTT_PTE_PAT4 BIT_ULL(61)
18 #define XE_PPGTT_PDE_PDPE_PAT2 BIT_ULL(12)
19 #define XE_PPGTT_PTE_PAT2 BIT_ULL(7)
20 #define XE_PPGTT_PTE_PAT1 BIT_ULL(4)
21 #define XE_PPGTT_PTE_PAT0 BIT_ULL(3)
23 #define XE_PDE_PS_2M BIT_ULL(7)
24 #define XE_PDPE_PS_1G BIT_ULL(7)
[all …]
/linux/drivers/net/ethernet/broadcom/bnge/
H A Dbnge.h41 BNGE_FW_CAP_SHORT_CMD = BIT_ULL(0),
42 BNGE_FW_CAP_LLDP_AGENT = BIT_ULL(1),
43 BNGE_FW_CAP_DCBX_AGENT = BIT_ULL(2),
44 BNGE_FW_CAP_IF_CHANGE = BIT_ULL(3),
45 BNGE_FW_CAP_KONG_MB_CHNL = BIT_ULL(4),
46 BNGE_FW_CAP_ERROR_RECOVERY = BIT_ULL(5),
47 BNGE_FW_CAP_PKG_VER = BIT_ULL(6),
48 BNGE_FW_CAP_CFA_ADV_FLOW = BIT_ULL(7),
49 BNGE_FW_CAP_CFA_RFS_RING_TBL_IDX_V2 = BIT_ULL(8),
50 BNGE_FW_CAP_PCIE_STATS_SUPPORTED = BIT_ULL(9),
[all …]
/linux/drivers/gpu/drm/arm/display/komeda/
H A Dkomeda_dev.h16 #define KOMEDA_EVENT_VSYNC BIT_ULL(0)
17 #define KOMEDA_EVENT_FLIP BIT_ULL(1)
18 #define KOMEDA_EVENT_URUN BIT_ULL(2)
19 #define KOMEDA_EVENT_IBSY BIT_ULL(3)
20 #define KOMEDA_EVENT_OVR BIT_ULL(4)
21 #define KOMEDA_EVENT_EOW BIT_ULL(5)
22 #define KOMEDA_EVENT_MODE BIT_ULL(6)
23 #define KOMEDA_EVENT_FULL BIT_ULL(7)
24 #define KOMEDA_EVENT_EMPTY BIT_ULL(8)
26 #define KOMEDA_ERR_TETO BIT_ULL(14)
[all …]
/linux/drivers/net/ethernet/marvell/octeon_ep_vf/
H A Doctep_vf_regs_cn9k.h20 #define CN93_VF_RING_OFFSET BIT_ULL(17)
69 #define CN93_VF_R_IN_CTL_IDLE BIT_ULL(28)
71 #define CN93_VF_R_IN_CTL_IS_64B BIT_ULL(24)
72 #define CN93_VF_R_IN_CTL_D_NSR BIT_ULL(8)
73 #define CN93_VF_R_IN_CTL_D_ESR BIT_ULL(6)
74 #define CN93_VF_R_IN_CTL_D_ROR BIT_ULL(5)
75 #define CN93_VF_R_IN_CTL_NSR BIT_ULL(3)
76 #define CN93_VF_R_IN_CTL_ESR BIT_ULL(1)
77 #define CN93_VF_R_IN_CTL_ROR BIT_ULL(0)
120 #define CN93_VF_R_OUT_INT_LEVELS_BMODE BIT_ULL(63)
[all …]
H A Doctep_vf_regs_cnxk.h128 #define CNXK_VF_R_OUT_INT_LEVELS_BMODE BIT_ULL(63)
131 #define CNXK_VF_R_OUT_CTL_IDLE BIT_ULL(40)
132 #define CNXK_VF_R_OUT_CTL_ES_I BIT_ULL(34)
133 #define CNXK_VF_R_OUT_CTL_NSR_I BIT_ULL(33)
134 #define CNXK_VF_R_OUT_CTL_ROR_I BIT_ULL(32)
135 #define CNXK_VF_R_OUT_CTL_ES_D BIT_ULL(30)
136 #define CNXK_VF_R_OUT_CTL_NSR_D BIT_ULL(29)
137 #define CNXK_VF_R_OUT_CTL_ROR_D BIT_ULL(28)
138 #define CNXK_VF_R_OUT_CTL_ES_P BIT_ULL(26)
139 #define CNXK_VF_R_OUT_CTL_NSR_P BIT_ULL(25)
[all …]
/linux/drivers/net/ethernet/mediatek/
H A Dmtk_eth_soc.h790 #define MT7623_CLKS_BITMAP (BIT_ULL(MTK_CLK_ETHIF) | BIT_ULL(MTK_CLK_ESW) | \
791 BIT_ULL(MTK_CLK_GP1) | BIT_ULL(MTK_CLK_GP2) | \
792 BIT_ULL(MTK_CLK_TRGPLL))
793 #define MT7622_CLKS_BITMAP (BIT_ULL(MTK_CLK_ETHIF) | BIT_ULL(MTK_CLK_ESW) | \
794 BIT_ULL(MTK_CLK_GP0) | BIT_ULL(MTK_CLK_GP1) | \
795 BIT_ULL(MTK_CLK_GP2) | \
796 BIT_ULL(MTK_CLK_SGMII_TX_250M) | \
797 BIT_ULL(MTK_CLK_SGMII_RX_250M) | \
798 BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \
799 BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \
[all …]
/linux/drivers/vdpa/pds/
H A Ddebugfs.c54 u64 mask = BIT_ULL(i); in print_feature_bits_all()
57 case BIT_ULL(VIRTIO_NET_F_CSUM): in print_feature_bits_all()
60 case BIT_ULL(VIRTIO_NET_F_GUEST_CSUM): in print_feature_bits_all()
63 case BIT_ULL(VIRTIO_NET_F_CTRL_GUEST_OFFLOADS): in print_feature_bits_all()
66 case BIT_ULL(VIRTIO_NET_F_MTU): in print_feature_bits_all()
69 case BIT_ULL(VIRTIO_NET_F_MAC): in print_feature_bits_all()
72 case BIT_ULL(VIRTIO_NET_F_GUEST_TSO4): in print_feature_bits_all()
75 case BIT_ULL(VIRTIO_NET_F_GUEST_TSO6): in print_feature_bits_all()
78 case BIT_ULL(VIRTIO_NET_F_GUEST_ECN): in print_feature_bits_all()
81 case BIT_ULL(VIRTIO_NET_F_GUEST_UFO): in print_feature_bits_all()
[all …]
/linux/tools/testing/selftests/kvm/include/x86/
H A Dpmu.h31 #define ARCH_PERFMON_EVENTSEL_USR BIT_ULL(16)
32 #define ARCH_PERFMON_EVENTSEL_OS BIT_ULL(17)
33 #define ARCH_PERFMON_EVENTSEL_EDGE BIT_ULL(18)
34 #define ARCH_PERFMON_EVENTSEL_PIN_CONTROL BIT_ULL(19)
35 #define ARCH_PERFMON_EVENTSEL_INT BIT_ULL(20)
36 #define ARCH_PERFMON_EVENTSEL_ANY BIT_ULL(21)
37 #define ARCH_PERFMON_EVENTSEL_ENABLE BIT_ULL(22)
38 #define ARCH_PERFMON_EVENTSEL_INV BIT_ULL(23)
42 #define INTEL_RDPMC_METRICS BIT_ULL(29)
43 #define INTEL_RDPMC_FIXED BIT_ULL(30)
[all …]
/linux/drivers/net/ethernet/marvell/octeontx2/af/
H A Drpm.h21 #define RPM_NIX0_RESET BIT_ULL(3)
22 #define RPMX_RX_TS_PREPEND BIT_ULL(22)
23 #define RPMX_TX_PTP_1S_SUPPORT BIT_ULL(17)
30 #define RPMX_MTI_PCS_LBK BIT_ULL(14)
36 #define RPMX_MTI_MAC100X_COMMAND_CONFIG_RX_P_DISABLE BIT_ULL(29)
37 #define RPMX_MTI_MAC100X_COMMAND_CONFIG_TX_P_DISABLE BIT_ULL(28)
38 #define RPMX_MTI_MAC100X_COMMAND_CONFIG_PAUSE_IGNORE BIT_ULL(8)
39 #define RPMX_MTI_MAC100X_COMMAND_CONFIG_PFC_MODE BIT_ULL(19)
57 #define RPMX_CMR_RX_OVR_BP_EN(x) BIT_ULL((x) + 8)
58 #define RPMX_CMR_RX_OVR_BP_BP(x) BIT_ULL((x) + 4)
[all …]
/linux/drivers/firmware/efi/
H A Dcper-x86.c11 #define VALID_LAPIC_ID BIT_ULL(0)
12 #define VALID_CPUID_INFO BIT_ULL(1)
29 #define INFO_VALID_CHECK_INFO BIT_ULL(0)
30 #define INFO_VALID_TARGET_ID BIT_ULL(1)
31 #define INFO_VALID_REQUESTOR_ID BIT_ULL(2)
32 #define INFO_VALID_RESPONDER_ID BIT_ULL(3)
33 #define INFO_VALID_IP BIT_ULL(4)
35 #define CHECK_VALID_TRANS_TYPE BIT_ULL(0)
36 #define CHECK_VALID_OPERATION BIT_ULL(1)
37 #define CHECK_VALID_LEVEL BIT_ULL(2)
[all …]
/linux/tools/arch/x86/include/asm/
H A Dmsr-index.h100 #define MSR_PLATFORM_INFO_CPUID_FAULT BIT_ULL(MSR_PLATFORM_INFO_CPUID_FAULT_BIT)
218 #define ARCH_CAP_ITS_NO BIT_ULL(62) /*
288 #define LBR_INFO_MISPRED BIT_ULL(63)
289 #define LBR_INFO_IN_TX BIT_ULL(62)
290 #define LBR_INFO_ABORT BIT_ULL(61)
291 #define LBR_INFO_CYC_CNT_VALID BIT_ULL(60)
324 #define PERF_CAP_PEBS_TRAP BIT_ULL(6)
325 #define PERF_CAP_ARCH_REG BIT_ULL(7)
327 #define PERF_CAP_FW_WRITES BIT_ULL(13)
328 #define PERF_CAP_PEBS_BASELINE BIT_ULL(14)
[all …]
/linux/drivers/net/ethernet/intel/iavf/
H A Diavf.h304 #define IAVF_FLAG_AQ_ENABLE_QUEUES BIT_ULL(0)
305 #define IAVF_FLAG_AQ_DISABLE_QUEUES BIT_ULL(1)
306 #define IAVF_FLAG_AQ_ADD_MAC_FILTER BIT_ULL(2)
307 #define IAVF_FLAG_AQ_ADD_VLAN_FILTER BIT_ULL(3)
308 #define IAVF_FLAG_AQ_DEL_MAC_FILTER BIT_ULL(4)
309 #define IAVF_FLAG_AQ_DEL_VLAN_FILTER BIT_ULL(5)
310 #define IAVF_FLAG_AQ_CONFIGURE_QUEUES BIT_ULL(6)
311 #define IAVF_FLAG_AQ_MAP_VECTORS BIT_ULL(7)
312 #define IAVF_FLAG_AQ_HANDLE_RESET BIT_ULL(8)
313 #define IAVF_FLAG_AQ_CONFIGURE_RSS BIT_ULL(9) /* direct AQ config */
[all …]
/linux/arch/x86/include/asm/shared/
H A Dtdx.h25 #define TDX_ATTR_DEBUG BIT_ULL(TDX_ATTR_DEBUG_BIT)
27 #define TDX_ATTR_HGS_PLUS_PROF BIT_ULL(TDX_ATTR_HGS_PLUS_PROF_BIT)
29 #define TDX_ATTR_PERF_PROF BIT_ULL(TDX_ATTR_PERF_PROF_BIT)
31 #define TDX_ATTR_PMT_PROF BIT_ULL(TDX_ATTR_PMT_PROF_BIT)
33 #define TDX_ATTR_ICSSD BIT_ULL(TDX_ATTR_ICSSD_BIT)
35 #define TDX_ATTR_LASS BIT_ULL(TDX_ATTR_LASS_BIT)
37 #define TDX_ATTR_SEPT_VE_DISABLE BIT_ULL(TDX_ATTR_SEPT_VE_DISABLE_BIT)
39 #define TDX_ATTR_MIGRTABLE BIT_ULL(TDX_ATTR_MIGRTABLE_BIT)
41 #define TDX_ATTR_PKS BIT_ULL(TDX_ATTR_PKS_BIT)
43 #define TDX_ATTR_KL BIT_ULL(TDX_ATTR_KL_BIT)
[all …]
/linux/drivers/gpu/drm/i915/
H A Di915_gem_gtt.h41 #define PIN_NOEVICT BIT_ULL(0)
42 #define PIN_NOSEARCH BIT_ULL(1)
43 #define PIN_NONBLOCK BIT_ULL(2)
44 #define PIN_MAPPABLE BIT_ULL(3)
45 #define PIN_ZONE_4G BIT_ULL(4)
46 #define PIN_HIGH BIT_ULL(5)
47 #define PIN_OFFSET_BIAS BIT_ULL(6)
48 #define PIN_OFFSET_FIXED BIT_ULL(7)
49 #define PIN_OFFSET_GUARD BIT_ULL(8)
50 #define PIN_VALIDATE BIT_ULL(9) /* validate placement only, no need to call unpin() */
[all …]
/linux/drivers/net/ethernet/cavium/liquidio/
H A Dcn66xx_regs.h367 #define CN6XXX_INTR_DMA0_FORCE BIT_ULL(32)
368 #define CN6XXX_INTR_DMA1_FORCE BIT_ULL(33)
369 #define CN6XXX_INTR_DMA0_COUNT BIT_ULL(34)
370 #define CN6XXX_INTR_DMA1_COUNT BIT_ULL(35)
371 #define CN6XXX_INTR_DMA0_TIME BIT_ULL(36)
372 #define CN6XXX_INTR_DMA1_TIME BIT_ULL(37)
373 #define CN6XXX_INTR_INSTR_DB_OF_ERR BIT_ULL(48)
374 #define CN6XXX_INTR_SLIST_DB_OF_ERR BIT_ULL(49)
375 #define CN6XXX_INTR_POUT_ERR BIT_ULL(50)
376 #define CN6XXX_INTR_PIN_BP_ERR BIT_ULL(51)
[all …]
H A Dcn23xx_pf_regs.h137 #define CN23XX_PKT_MAC_CTL_RINFO_TRS BIT_ULL(16)
186 #define CN23XX_PKT_INPUT_CTL_VF_NUM BIT_ULL(32)
233 #define CN23XX_IN_DONE_CNTS_PI_INT BIT_ULL(62)
234 #define CN23XX_IN_DONE_CNTS_CINT_ENB BIT_ULL(48)
389 #define CN23XX_MSIX_ENTRY_VECTOR_CTL BIT_ULL(32)
425 #define CN23XX_INTR_PO_INT BIT_ULL(63)
426 #define CN23XX_INTR_PI_INT BIT_ULL(62)
427 #define CN23XX_INTR_MBOX_INT BIT_ULL(61)
428 #define CN23XX_INTR_RESEND BIT_ULL(60)
430 #define CN23XX_INTR_CINT_ENB BIT_ULL(48)
[all …]
/linux/drivers/net/ethernet/marvell/octeon_ep/
H A Doctep_regs_cn9k_pf.h157 #define CN93_R_OUT_INT_LEVELS_BMODE BIT_ULL(63)
160 #define CN93_R_OUT_CTL_IDLE BIT_ULL(40)
161 #define CN93_R_OUT_CTL_ES_I BIT_ULL(34)
162 #define CN93_R_OUT_CTL_NSR_I BIT_ULL(33)
163 #define CN93_R_OUT_CTL_ROR_I BIT_ULL(32)
164 #define CN93_R_OUT_CTL_ES_D BIT_ULL(30)
165 #define CN93_R_OUT_CTL_NSR_D BIT_ULL(29)
166 #define CN93_R_OUT_CTL_ROR_D BIT_ULL(28)
167 #define CN93_R_OUT_CTL_ES_P BIT_ULL(26)
168 #define CN93_R_OUT_CTL_NSR_P BIT_ULL(25)
[all …]
H A Doctep_regs_cnxk_pf.h162 #define CNXK_R_OUT_INT_LEVELS_BMODE BIT_ULL(63)
165 #define CNXK_R_OUT_CTL_IDLE BIT_ULL(40)
166 #define CNXK_R_OUT_CTL_ES_I BIT_ULL(34)
167 #define CNXK_R_OUT_CTL_NSR_I BIT_ULL(33)
168 #define CNXK_R_OUT_CTL_ROR_I BIT_ULL(32)
169 #define CNXK_R_OUT_CTL_ES_D BIT_ULL(30)
170 #define CNXK_R_OUT_CTL_NSR_D BIT_ULL(29)
171 #define CNXK_R_OUT_CTL_ROR_D BIT_ULL(28)
172 #define CNXK_R_OUT_CTL_ES_P BIT_ULL(26)
173 #define CNXK_R_OUT_CTL_NSR_P BIT_ULL(25)
[all …]

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