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Searched refs:BIT_U64 (Results 1 – 5 of 5) sorted by relevance

/linux/drivers/gpu/drm/panthor/
H A Dpanthor_regs.h232 #define PWR_STATUS_ALLOW_L2 BIT_U64(0)
233 #define PWR_STATUS_ALLOW_TILER BIT_U64(1)
234 #define PWR_STATUS_ALLOW_SHADER BIT_U64(8)
235 #define PWR_STATUS_ALLOW_BASE BIT_U64(14)
236 #define PWR_STATUS_ALLOW_STACK BIT_U64(15)
237 #define PWR_STATUS_DOMAIN_ALLOWED(x) BIT_U64(x)
238 #define PWR_STATUS_DELEGATED_L2 BIT_U64(16)
239 #define PWR_STATUS_DELEGATED_TILER BIT_U64(17)
240 #define PWR_STATUS_DELEGATED_SHADER BIT_U64(24)
241 #define PWR_STATUS_DELEGATED_BASE BIT_U64(30)
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/linux/drivers/accel/amdxdna/
H A Dnpu4_regs.c69 { 14, 0, AIE2_RT_CFG_INIT, BIT_U64(AIE2_PREEMPT) }, /* Frame boundary preemption */
93 { .features = BIT_U64(AIE2_NPU_COMMAND), .major = 6, .min_minor = 15 },
94 { .features = BIT_U64(AIE2_PREEMPT), .major = 6, .min_minor = 12 },
95 { .features = BIT_U64(AIE2_TEMPORAL_ONLY), .major = 6, .min_minor = 12 },
96 { .features = BIT_U64(AIE2_APP_HEALTH), .major = 6, .min_minor = 18 },
H A Dnpu1_regs.c70 { .features = BIT_U64(AIE2_NPU_COMMAND), .major = 5, .min_minor = 8 },
/linux/tools/include/linux/
H A Dbits.h76 #define BIT_U64(nr) BIT_TYPE(u64, nr) macro
/linux/drivers/media/i2c/ccs/
H A Dccs-core.c1213 sensor->default_mbus_frame_fmts |= BIT_U64(j); in ccs_get_mbus_formats()
1246 if (!(sensor->default_mbus_frame_fmts & BIT_U64(i))) in ccs_get_mbus_formats()
2096 if (sensor->mbus_frame_fmts & BIT_U64(i) && in ccs_validate_csi_data_format()
2126 if (sensor->mbus_frame_fmts & BIT_U64(i)) in ccs_enum_mbus_code()