Searched refs:BIT_5 (Results 1 – 15 of 15) sorted by relevance
85 #define OF_EXPL_CONF BIT_5 /* Explicit Confirmation Requested */179 #define NOTIFY_ACK_FLAGS_FCSP BIT_5481 #define CTIO7_FLAGS_EXPLICIT_CONFORM BIT_5752 #define NOTIFY_ACK_CLEAR_LIP_RESET BIT_5857 TRC_XMIT_STATUS = BIT_5,
23 #define FO2_ENABLE_SEL_CLASS2 BIT_543 #define PDF_FCP2_CONF BIT_5908 #define LCF_SKIP_PRLI BIT_5 /* Skip PRLI after PLOGI. */909 #define LCF_IMPL_LOGO_ALL BIT_5 /* Implicit LOGO to all ports. */1188 #define CSRX_MAX_WRT_BURST_MASK (BIT_5|BIT_4)1229 #define HCCRX_RISC_RESET BIT_5 /* RISC Reset mode bit. */1510 VP_FLAGS_NAME_VALID = BIT_5,
4528 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4; in qla2x00_update_fw_options()4535 ha->fw_options[10] |= BIT_5 | in qla2x00_update_fw_options()4541 (BIT_7 | BIT_6 | BIT_5)) >> 5; in qla2x00_update_fw_options()4546 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4; in qla2x00_update_fw_options()4553 ha->fw_options[11] |= BIT_5 | in qla2x00_update_fw_options()5298 nv->firmware_options[1] = BIT_7 | BIT_5; in qla2x00_nvram_config()5299 nv->add_firmware_options[0] = BIT_5; in qla2x00_nvram_config()5300 nv->add_firmware_options[1] = BIT_5 | BIT_4; in qla2x00_nvram_config()5305 nv->firmware_options[1] = BIT_7 | BIT_5; in qla2x00_nvram_config()5306 nv->add_firmware_options[0] = BIT_5; in qla2x00_nvram_config()[all …]
760 options |= BIT_5; in qla25xx_create_req_que()878 options |= BIT_5; in qla25xx_create_rsp_que()
7988 nv->firmware_options_1 |= cpu_to_le32(BIT_5); in qlt_24xx_config_nvram_stage1()8015 tmp = ~(BIT_4|BIT_5|BIT_6); in qlt_24xx_config_nvram_stage1()8094 nv->firmware_options_1 |= cpu_to_le32(BIT_5); in qlt_81xx_config_nvram_stage1()8119 tmp = ~(BIT_4|BIT_5|BIT_6); in qlt_81xx_config_nvram_stage1()8197 vpmod->options_idx1 &= ~BIT_5; in qlt_modify_vp_config()
2585 } else if (iop[0] & BIT_5) in qla24xx_logio_entry()
6172 if (sfp[0] & BIT_2 || sfp[1] & (BIT_6|BIT_5)) in qla24xx_process_purex_rdp()
22 #define BIT_5 0x20 macro127 #define ISP_CFG1_F64 BIT_4|BIT_5 /* 128-byte FIFO threshold */128 #define ISP_CFG1_F32 BIT_5 /* 128-byte FIFO threshold */311 #define TP_PPR BIT_5 /* PPR */
1372 arg1 |= (BIT_2 | BIT_5); in qlcnic_config_switch_port()1376 arg1 |= (BIT_3 | BIT_5); in qlcnic_config_switch_port()1427 esw_cfg->host_vlan_tag = !!(arg1 & BIT_5); in qlcnic_get_eswitch_port_config()
200 #define BIT_5 0x20 macro
28 #define QLCNIC_DUMP_RD_SAVE BIT_5
923 #define QLCNIC_FW_CAPABILITY_SET_DRV_VER BIT_5
389 if (status & BIT_5) in qlcnic_sriov_get_vf_vport_info()
368 #define QLCNIC_ENCAP_DO_L4_CSUM BIT_5
85 #define BIT_5 0x20 macro