Searched refs:BIT_3 (Results 1 – 19 of 19) sorted by relevance
456 #define BD_WRAP_BACK BIT_3496 #define CF_DIF_SEG_DESCR_ENABLE BIT_3813 #define ECF_SEC_LOGIN BIT_3972 #define TCF_ABORT_TASK_SET BIT_31003 #define AOF_ABTS_RTY_CNT BIT_3 /* Use driver specified retry count. */1199 #define ICRX_EN_RISC_INT BIT_3 /* Enable RISC interrupts on PCI. */1202 #define ISRX_RISC_INT BIT_3 /* RISC interrupt. */1257 #define GPDX_LED_COLOR_MASK (BIT_4|BIT_3|BIT_2)1262 #define GPDX_LED_GREEN_ON BIT_31395 #define MDBS_NON_PARTIC BIT_3[all …]
63 #define CF_DIF_SEG_DESCR_ENABLE BIT_3
180 #define NOTIFY_ACK_FLAGS_TERMINATE BIT_3513 #define CTIO_CRC2_AF_DIF_DSD_ENA BIT_3855 TRC_XFR_RDY = BIT_3,
1177 mb[1] = BIT_2 | BIT_3; in qla24xx_async_gnl()4524 (BIT_4 | BIT_3)) >> 3; in qla2x00_update_fw_options()4526 (BIT_3 | BIT_2 | BIT_1 | BIT_0); in qla2x00_update_fw_options()4544 (BIT_3 | BIT_2 | BIT_1 | BIT_0); in qla2x00_update_fw_options()4572 ha->fw_options[2] |= BIT_3; in qla2x00_update_fw_options()4597 ha->fw_options[2] |= BIT_3; in qla24xx_update_fw_options()5310 nv->firmware_options[0] = BIT_3 | BIT_1; in qla2x00_nvram_config()5353 nv->firmware_options[0] &= ~BIT_3; in qla2x00_nvram_config()5431 ha->flags.enable_target_reset = ((nv->host_p[1] & BIT_3) ? 1 : 0); in qla2x00_nvram_config()5506 icb->firmware_options[0] &= ~BIT_3; in qla2x00_nvram_config()[all …]
389 RESOURCE_HA = BIT_3,
1385 options |= BIT_3|BIT_2|BIT_1; in qla2x00_beacon_config_store()1402 options |= BIT_3; in qla2x00_beacon_config_store()
4225 if (rd_reg_dword(®->iobase_c8) & BIT_3) in qla2xxx_check_risc_status()
20 #define BIT_3 0x8 macro148 #define NV_DATA_IN BIT_3156 #define CDMA_CONF_SENAB BIT_3 /* SXP to DMA Data enable */173 #define DDMA_CONF_SENAB BIT_3 /* SXP to DMA Data enable */569 #define RF_BAD_PAYLOAD BIT_3 /* Bad payload. */
1348 arg1 &= ~(BIT_2 | BIT_3); in qlcnic_config_switch_port()1354 arg2 |= (BIT_2 | BIT_3); in qlcnic_config_switch_port()1364 arg2 &= ~(BIT_1 | BIT_2 | BIT_3); in qlcnic_config_switch_port()1368 arg2 &= ~BIT_3; in qlcnic_config_switch_port()1376 arg1 |= (BIT_3 | BIT_5); in qlcnic_config_switch_port()
198 #define BIT_3 0x8 macro495 #define TA_CTL_BUSY BIT_3
922 #define QLCNIC_FW_CAP2_HW_LRO_IPV6 BIT_31317 #define QLCNIC_SWITCH_PROMISC_MODE BIT_3
553 if (mbx_out & BIT_3) in qlcnic_83xx_dcb_get_hw_capability()
26 #define QLCNIC_DUMP_ORCRB BIT_3
703 cmd.req.arg[2] |= BIT_1 | BIT_3 | BIT_8; in qlcnic_sriov_set_vf_acl()
1024 #define QLC_83XX_SET_VXLAN_UDP_DPORT BIT_3
385 if (status & BIT_3) in qlcnic_sriov_get_vf_vport_info()
366 #define QLCNIC_ENCAP_INNER_L4_UDP BIT_3
2022 lro_bit_mask = (mode ? (BIT_0 | BIT_1 | BIT_2 | BIT_3) : 0); in qlcnic_83xx_config_hw_lro()
83 #define BIT_3 0x8 macro240 #define SRB_DMA_VALID BIT_3 /* DMA Buffer mapped. */