Searched refs:BCLR (Results 1 – 16 of 16) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVScheduleZb.td | 34 def WriteSingleBit : SchedWrite; // BCLR/BSET/BINV 73 def ReadSingleBit : SchedRead; // BCLR/BSET/BINV/BEXT
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| H A D | RISCVInstrInfoZb.td | 323 def BCLR : ALU_rr<0b0100100, 0b001, "bclr">, 529 (BCLR GPR:$rs1, GPR:$rs2)>; 531 (BCLR GPR:$rs1, GPR:$rs2)>;
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| H A D | RISCVOptWInstrs.cpp | 256 case RISCV::BCLR: in hasAllNBitUsers()
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| H A D | RISCVInstrInfoXCV.td | 719 defm BCLR : PatCoreVBitManip<int_riscv_cv_bitmanip_bclr>;
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| H A D | RISCVISelDAGToDAG.cpp | 3692 case RISCV::BCLR: in hasAllNBitUsers()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCReduceCRLogicals.cpp | 165 : OrigBROpcode == PPC::BCLR ? PPC::BCLRn : PPC::BCLR; in splitMBB() 282 if (BROp == PPC::BC || BROp == PPC::BCLR) { in computeBranchTargetAndInversion() 512 if (Opc == PPC::BC || Opc == PPC::BCn || Opc == PPC::BCLR || in createCRLogicalOpInfo()
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| H A D | PPCEarlyReturn.cpp | 100 TII->get(J->getOpcode() == PPC::BC ? PPC::BCLR : PPC::BCLRn)); in processBlock()
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| H A D | PPCMacroFusion.def | 154 FUSION_OP_SET(BCLR, BCLRn, gBCLR, BCLRL, BCLRLn, gBCLRL))
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| H A D | PPCScheduleP7.td | 123 BDZLR, BDZLR8, BDZLRL, BDZLRLm, BLR, BLR8, BLRL, BCL, BCLR, BCLRL, BCLRLn,
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| H A D | P10InstrResources.td | 317 BCLR, BCLRn, BDNZLR, BDNZLR8, BDNZLRm, BDNZLRp, BDZLR, BDZLR8, BDZLRm, BDZLRp, gBCLR,
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| H A D | P9InstrResources.td | 1313 (instregex "BCLR(L)?(n)?$"),
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| H A D | PPCInstrInfo.cpp | 2213 MI.setDesc(get(PPC::BCLR)); in PredicateInstruction()
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| H A D | PPCInstrInfo.td | 1411 def BCLR : XLForm_2_br2<19, 16, 12, 0, (outs), (ins crbitrc:$BI),
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| /freebsd/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kInstrBits.td | 15 /// BCHG [~] BCLR [~] BSET [~] BTST [~] 127 defm BCLR : MxBIT<"bclr", 0b110, 0b010>;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsScheduleP5600.td | 300 def : InstRW<[P5600WriteMSAShortInt], (instregex "^(BCLR|BCLRI)_[BHWD]$")>;
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| H A D | MipsScheduleGeneric.td | 1450 def : InstRW<[GenericWriteMSAShortInt], (instregex "^(BCLR|BCLRI)_[BHWD]$")>;
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