| /linux/tools/testing/selftests/net/ |
| H A D | udpgro_fwd.sh | 7 readonly BASE="ns-$(mktemp -u XXXXXX)"
11 readonly NS_SRC=$BASE$SRC
12 readonly NS_DST=$BASE$DST
51 ip link set dev veth$ns netns $BASE$ns
52 ip -n $BASE$ns link set dev veth$ns up
53 ip -n $BASE$ns addr add dev veth$ns $BM_NET_V4$ns/24
54 ip -n $BASE$ns addr add dev veth$ns $BM_NET_V6$ns/64 nodad
80 create_vxlan_endpoint $BASE$ns veth$ns $BM_NET_V4$((3 - $ns)) vxlan$ns 4
81 ip -n $BASE$ns addr add dev vxlan$ns $OL_NET_V4$ns/24
84 create_vxlan_endpoint $BASE$ns veth$ns $BM_NET_V6$((3 - $ns)) vxlan6$ns 6
[all …]
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| /linux/Documentation/driver-api/media/drivers/ |
| H A D | radiotrack.rst | 129 Default: BASE <-- 0xc8 (current volume, no stereo detect,
132 Card Off: BASE <-- 0x00 (audio mute, no stereo detect,
135 Card On: BASE <-- 0x00 (see "Card Off", clears any unfinished business)
136 BASE <-- 0xc8 (see "Default")
138 Volume Down: BASE <-- 0x48 (volume down, no stereo detect,
141 BASE <-- 0xc8 (see "Default")
143 Volume Up: BASE <-- 0x88 (volume up, no stereo detect,
146 BASE <-- 0xc8 (see "Default")
148 Check Stereo: BASE <-- 0xd8 (current volume, stereo detect,
151 x <-- BASE (read ioport)
[all …]
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| /linux/drivers/media/pci/cobalt/ |
| H A D | cobalt-omnitek.c | 42 #define BASE (cobalt->bar0) macro
43 #define CAPABILITY_HEADER (BASE)
44 #define CAPABILITY_REGISTER (BASE + 0x04)
47 #define INTERRUPT_STATUS (BASE + 0x08)
48 #define PCI(c) (BASE + 0x40 + ((c) * 0x40))
49 #define SIZE(c) (BASE + 0x58 + ((c) * 0x40))
50 #define DESCRIPTOR(c) (BASE + 0x50 + ((c) * 0x40))
51 #define CS_REG(c) (BASE + 0x60 + ((c) * 0x40))
52 #define BYTES_TRANSFERRED(c) (BASE + 0x64 + ((c) * 0x40))
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| /linux/tools/testing/selftests/gpio/ |
| H A D | gpio-mockup.sh | 9 BASE=${0%/*}
106 $BASE/gpio-mockup-cdev $cdev_opts /dev/$chip $offset
150 $BASE/gpio-mockup-cdev $cdev_opts -s$val /dev/$chip $offset &
158 $BASE/gpio-mockup-cdev $cdev_opts /dev/$chip $offset || true
343 source $BASE/gpio-mockup-sysfs.sh
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| /linux/include/linux/ |
| H A D | zutil.h | 53 #define BASE 65521L /* largest prime smaller than 65536 */ macro
100 s1 %= BASE; in zlib_adler32()
101 s2 %= BASE; in zlib_adler32()
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| /linux/tools/perf/tests/shell/ |
| H A D | daemon.sh | 168 base=BASE
223 base=BASE
250 base=BASE
285 base=BASE
348 base=BASE
406 base=BASE
461 base=BASE
502 base=BASE
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| /linux/arch/sparc/net/ |
| H A D | bpf_jit_comp_32.c | 181 #define emit_loadptr(BASE, STRUCT, FIELD, DEST) \ argument
184 *prog++ = LDPTRI | RS1(BASE) | S13(_off) | RD(DEST); \
187 #define emit_load32(BASE, STRUCT, FIELD, DEST) \ argument
190 *prog++ = LD32I | RS1(BASE) | S13(_off) | RD(DEST); \
193 #define emit_load16(BASE, STRUCT, FIELD, DEST) \ argument
196 *prog++ = LD16I | RS1(BASE) | S13(_off) | RD(DEST); \
199 #define __emit_load8(BASE, STRUCT, FIELD, DEST) \ argument
201 *prog++ = LD8I | RS1(BASE) | S13(_off) | RD(DEST); \
204 #define emit_load8(BASE, STRUCT, FIELD, DEST) \ argument
206 __emit_load8(BASE, STRUCT, FIELD, DEST); \
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/gpio/dce120/ |
| H A D | hw_factory_dce120.c | 57 #define BASE(seg) \ macro
61 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
64 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
|
| /linux/drivers/ps3/ |
| H A D | ps3av_cmd.c | 489 #define BASE PS3AV_CMD_AUDIO_FS_44K macro
493 [PS3AV_CMD_AUDIO_FS_44K-BASE] = { 6272, 6272, 17836, 17836, 8918 },
494 [PS3AV_CMD_AUDIO_FS_48K-BASE] = { 6144, 6144, 11648, 11648, 5824 },
495 [PS3AV_CMD_AUDIO_FS_88K-BASE] = { 12544, 12544, 35672, 35672, 17836 },
496 [PS3AV_CMD_AUDIO_FS_96K-BASE] = { 12288, 12288, 23296, 23296, 11648 },
497 [PS3AV_CMD_AUDIO_FS_176K-BASE] = { 25088, 25088, 71344, 71344, 35672 },
498 [PS3AV_CMD_AUDIO_FS_192K-BASE] = { 24576, 24576, 46592, 46592, 23296 }
540 ns_val = ps3av_ns_table[PS3AV_CMD_AUDIO_FS_44K-BASE][d]; in ps3av_cnv_ns()
547 #undef BASE
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| /linux/drivers/gpu/drm/amd/display/dc/gpio/dcn10/ |
| H A D | hw_factory_dcn10.c | 54 #define BASE(seg) \ macro
58 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
61 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
|
| /linux/drivers/media/tuners/ |
| H A D | xc2028-types.h | 14 #define BASE (1<<0) macro
15 #define BASE_TYPES (BASE|F8MHZ|MTS|FM|INPUT1|INPUT2|INIT1)
|
| H A D | xc4000.c | 552 if (type & BASE) in dump_firm_type_and_int_freq()
641 & (BASE | INIT1 | FM | DTV6 | DTV7 | DTV78 | DTV8 | SCODE)) in seek_firmware()
960 if (priv->cur_fw.type & BASE) { in check_firmware()
975 rc = load_firmware(fe, BASE, &std0); in check_firmware()
984 rc = load_firmware(fe, BASE | INIT1, &std0); in check_firmware()
986 rc = load_firmware(fe, BASE | INIT1, &std0); in check_firmware()
998 if (priv->cur_fw.type == (BASE | new_fw.type) && in check_firmware()
1070 priv->cur_fw.type |= BASE; in check_firmware()
1523 & (BASE | FM | DTV6 | DTV7 | DTV78 | DTV8)) == BASE) { in xc4000_get_frequency()
1556 if (priv->cur_fw.type & BASE) in xc4000_get_status()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/gpio/dcn21/ |
| H A D | hw_factory_dcn21.c | 53 #define BASE(seg) BASE_INNER(seg) macro
58 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
64 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
|
| /linux/drivers/gpu/drm/amd/display/dc/gpio/dcn32/ |
| H A D | hw_factory_dcn32.c | 55 #define BASE(seg) BASE_INNER(seg) macro
60 BASE(reg ## reg_name ## _BASE_IDX) + reg ## reg_name
66 BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
|
| /linux/drivers/gpu/drm/amd/display/dc/gpio/dcn30/ |
| H A D | hw_factory_dcn30.c | 62 #define BASE(seg) BASE_INNER(seg) macro
67 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
73 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
|
| /linux/drivers/gpu/drm/amd/display/dc/gpio/dcn315/ |
| H A D | hw_factory_dcn315.c | 59 #define BASE(seg) BASE_INNER(seg) macro
64 BASE(reg ## reg_name ## _BASE_IDX) + reg ## reg_name
70 BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
|
| /linux/drivers/gpu/drm/amd/display/dc/gpio/dcn20/ |
| H A D | hw_factory_dcn20.c | 55 #define BASE(seg) BASE_INNER(seg) macro
60 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
66 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
|
| /linux/drivers/gpu/drm/amd/display/dc/gpio/dcn401/ |
| H A D | hw_factory_dcn401.c | 35 #define BASE(seg) BASE_INNER(seg) macro
40 BASE(reg ## reg_name ## _BASE_IDX) + reg ## reg_name
46 BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
|
| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/ |
| H A D | dcn351_clk_mgr.c | 100 #define BASE(seg) BASE_INNER(seg) macro
103 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
|
| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn35/ |
| H A D | dcn35_resource.c | 129 #define BASE(seg) BASE_INNER(seg) macro
132 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
136 REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
142 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
146 REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
150 REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
153 REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
157 REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
161 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
165 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn351/ |
| H A D | dcn351_resource.c | 109 #define BASE(seg) BASE_INNER(seg) macro
112 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
116 REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
122 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
126 REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
130 REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
133 REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
137 REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
141 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
145 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn321/ |
| H A D | dcn321_resource.c | 115 #define BASE(seg) BASE_INNER(seg) macro
118 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
121 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
127 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
131 REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
135 REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
138 REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
142 REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
146 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
149 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dcn10/ |
| H A D | dcn10_dwb.h | 31 #define BASE(seg) \ macro
35 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
39 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
44 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
|
| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn401/ |
| H A D | dcn401_resource.c | 100 #define BASE(seg) BASE_INNER(seg) macro
103 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
106 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
112 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
116 REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
123 REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## reg_name ## _BASE_IDX) + \
126 REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
129 REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
133 REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
137 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
[all …]
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| /linux/arch/sparc/kernel/ |
| H A D | sun4v_tlb_miss.S | 11 #define LOAD_ITLB_INFO(BASE, VADDR, CTX) \ argument
12 ldx [BASE + HV_FAULT_I_ADDR_OFFSET], VADDR; \
13 ldx [BASE + HV_FAULT_I_CTX_OFFSET], CTX;
16 #define LOAD_DTLB_INFO(BASE, VADDR, CTX) \ argument
17 ldx [BASE + HV_FAULT_D_ADDR_OFFSET], VADDR; \
18 ldx [BASE + HV_FAULT_D_CTX_OFFSET], CTX;
|