Searched refs:A_PL_ENABLE (Results 1 – 6 of 6) sorted by relevance
73 u32 tp_intr = readl(tp->adapter->regs + A_PL_ENABLE); in t1_tp_intr_enable()81 tp->adapter->regs + A_PL_ENABLE); in t1_tp_intr_enable()88 tp->adapter->regs + A_PL_ENABLE); in t1_tp_intr_enable()94 u32 tp_intr = readl(tp->adapter->regs + A_PL_ENABLE); in t1_tp_intr_disable()101 tp->adapter->regs + A_PL_ENABLE); in t1_tp_intr_disable()107 tp->adapter->regs + A_PL_ENABLE); in t1_tp_intr_disable()
110 u32 enable, pl_intr = readl(espi->adapter->regs + A_PL_ENABLE); in t1_espi_intr_enable()121 writel(pl_intr | F_PL_INTR_ESPI, espi->adapter->regs + A_PL_ENABLE); in t1_espi_intr_enable()133 u32 pl_intr = readl(espi->adapter->regs + A_PL_ENABLE); in t1_espi_intr_disable()136 writel(pl_intr & ~F_PL_INTR_ESPI, espi->adapter->regs + A_PL_ENABLE); in t1_espi_intr_disable()
779 u32 pl_intr = readl(adapter->regs + A_PL_ENABLE); in t1_interrupts_enable()787 writel(pl_intr, adapter->regs + A_PL_ENABLE); in t1_interrupts_enable()809 writel(0, adapter->regs + A_PL_ENABLE); in t1_interrupts_disable()876 adapter->regs + A_PL_ENABLE); in asic_slow_intr()
145 pl_intr = readl(cmac->adapter->regs + A_PL_ENABLE); in pm3393_interrupt_enable()147 writel(pl_intr, cmac->adapter->regs + A_PL_ENABLE); in pm3393_interrupt_enable()
902 u32 val = readl(sge->adapter->regs + A_PL_ENABLE); in t1_sge_intr_disable()904 writel(val & ~SGE_PL_INTR_MASK, sge->adapter->regs + A_PL_ENABLE); in t1_sge_intr_disable()914 u32 val = readl(sge->adapter->regs + A_PL_ENABLE); in t1_sge_intr_enable()919 writel(val | SGE_PL_INTR_MASK, sge->adapter->regs + A_PL_ENABLE); in t1_sge_intr_enable()1646 adapter->regs + A_PL_ENABLE); in t1_interrupt_thread()
1735 #define A_PL_ENABLE 0xa00 macro