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Searched refs:APMU_SDH0 (Results 1 – 4 of 4) sorted by relevance

/linux/drivers/clk/mmp/
H A Dclk-pxa1908-apmu.c18 #define APMU_SDH0 0x54 macro
57 … "sdh0_clk", "sdh0_mix_clk", CLK_SET_RATE_PARENT | CLK_SET_RATE_UNGATE, APMU_SDH0, 0x12, 0x12, 0x0…
69 sdh_mix_config.reg_info.reg_clk_ctrl = pxa_unit->base + APMU_SDH0; in pxa1908_axi_periph_clk_init()
H A Dclk-of-pxa168.c46 #define APMU_SDH0 0x54 macro
234 …{0, "sdh0_mux", sdh_parent_names, ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, APMU_SDH0, 6,…
251 …{PXA168_CLK_SDH0, "sdh0_clk", "sdh0_mux", CLK_SET_RATE_PARENT, APMU_SDH0, 0x12, 0x12, 0x0, 0, &sdh…
256 …{PXA168_CLK_SDH01_AXI, "sdh01_axi_clk", NULL, CLK_SET_RATE_PARENT, APMU_SDH0, 0x9, 0x9, 0x0, 0, &s…
H A Dclk-of-pxa910.c39 #define APMU_SDH0 0x54 macro
195 …{0, "sdh0_mux", sdh_parent_names, ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, APMU_SDH0, 6,…
211 …{PXA910_CLK_SDH0, "sdh0_clk", "sdh0_mux", CLK_SET_RATE_PARENT, APMU_SDH0, 0x1b, 0x1b, 0x0, 0, &sdh…
H A Dclk-of-mmp2.c51 #define APMU_SDH0 0x54 macro
366 …{MMP2_CLK_SDH0, "sdh0_clk", "sdh_mix_clk", CLK_SET_RATE_PARENT, APMU_SDH0, 0x1b, 0x1b, 0x0, 0, &sd…
400 sdh_mix_config.reg_info.reg_clk_ctrl = pxa_unit->apmu_base + APMU_SDH0; in mmp2_axi_periph_clk_init()