Searched refs:ANALOGIX_DP_LN0_LINK_TRAINING_CTL (Results 1 – 2 of 2) sorted by relevance
80 #define ANALOGIX_DP_LN0_LINK_TRAINING_CTL 0x68C macro
552 dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL + 4 * lane); in analogix_dp_set_lane_link_training()557 return readl(dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL + 4 * lane); in analogix_dp_get_lane_link_training()