Home
last modified time | relevance | path

Searched refs:AMDGPU_VCN_CONTEXT_SIZE (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_vcn.h30 #define AMDGPU_VCN_CONTEXT_SIZE (512*1024) macro
H A Dvcn_v4_0_3.c428 AMDGPU_VCN_CONTEXT_SIZE); in vcn_v4_0_3_mc_resume()
535 VCN, 0, regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
998 regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE); in vcn_v4_0_3_start_sriov()
H A Dvcn_v5_0_0.c374 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); in vcn_v5_0_0_mc_resume()
474 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); in vcn_v5_0_0_mc_resume_dpg_mode()
H A Dvcn_v2_0.c417 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); in vcn_v2_0_mc_resume()
507 UVD, 0, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
1991 AMDGPU_VCN_CONTEXT_SIZE); in vcn_v2_0_start_sriov()
H A Dvcn_v4_0.c462 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); in vcn_v4_0_mc_resume()
561 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
1394 AMDGPU_VCN_CONTEXT_SIZE); in vcn_v4_0_start_sriov()
H A Dvcn_v2_5.c504 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); in vcn_v2_5_mc_resume()
593 VCN, 0, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
1351 AMDGPU_VCN_CONTEXT_SIZE); in vcn_v2_5_sriov_start()
H A Dvcn_v4_0_5.c410 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); in vcn_v4_0_5_mc_resume()
515 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); in vcn_v4_0_5_mc_resume_dpg_mode()
H A Dvcn_v3_0.c531 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); in vcn_v3_0_mc_resume()
619 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
1435 AMDGPU_VCN_CONTEXT_SIZE); in vcn_v3_0_start_sriov()
H A Dvcn_v1_0.c385 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); in vcn_v1_0_mc_resume_spg_mode()
459 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE, in vcn_v1_0_mc_resume_dpg_mode()
H A Damdgpu_vcn.c184 bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_CONTEXT_SIZE; in amdgpu_vcn_sw_init()