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Searched refs:AMDGPU_UVD_FIRMWARE_OFFSET (Results 1 – 11 of 11) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_uvd.h32 #define AMDGPU_UVD_FIRMWARE_OFFSET 256 macro
38 8) - AMDGPU_UVD_FIRMWARE_OFFSET)
H A Dvcn_v5_0_2.c343 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); in vcn_v5_0_2_mc_resume()
424 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); in vcn_v5_0_2_mc_resume_dpg_mode()
H A Dvcn_v5_0_1.c446 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); in vcn_v5_0_1_mc_resume()
527 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); in vcn_v5_0_1_mc_resume_dpg_mode()
857 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); in vcn_v5_0_1_start_sriov()
H A Duvd_v3_1.c250 addr = (adev->uvd.inst->gpu_addr + AMDGPU_UVD_FIRMWARE_OFFSET) >> 3; in uvd_v3_1_mc_resume()
H A Dvcn_v4_0_3.c500 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); in vcn_v4_0_3_mc_resume()
588 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
1086 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); in vcn_v4_0_3_start_sriov()
H A Dvcn_v5_0_0.c386 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, AMDGPU_UVD_FIRMWARE_OFFSET >> 3); in vcn_v5_0_0_mc_resume()
465 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); in vcn_v5_0_0_mc_resume_dpg_mode()
H A Dvcn_v4_0.c471 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, AMDGPU_UVD_FIRMWARE_OFFSET >> 3); in vcn_v4_0_mc_resume()
549 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
1413 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); in vcn_v4_0_start_sriov()
H A Dvcn_v3_0.c542 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); in vcn_v3_0_mc_resume()
610 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
1458 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); in vcn_v3_0_start_sriov()
H A Dvcn_v2_5.c614 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); in vcn_v2_5_mc_resume()
682 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
1458 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); in vcn_v2_5_sriov_start()
H A Dvcn_v4_0_5.c422 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, AMDGPU_UVD_FIRMWARE_OFFSET >> 3); in vcn_v4_0_5_mc_resume()
503 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); in vcn_v4_0_5_mc_resume_dpg_mode()
H A Dvcn_v2_0.c405 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); in vcn_v2_0_mc_resume()
475 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()