Searched refs:AMDGPU_SDMA_IRQ_INSTANCE0 (Results 1 – 12 of 12) sorted by relevance
32 AMDGPU_SDMA_IRQ_INSTANCE0 = 0, enumerator
499 (i == 0) ? AMDGPU_SDMA_IRQ_INSTANCE0 : in si_dma_sw_init()588 case AMDGPU_SDMA_IRQ_INSTANCE0: in si_dma_set_trap_irq_state()
110 AMDGPU_SDMA_IRQ_INSTANCE0 + i); in amdgpu_sdma_ras_late_init()
1405 AMDGPU_SDMA_IRQ_INSTANCE0 + i, in sdma_v4_4_2_sw_init()1426 AMDGPU_SDMA_IRQ_INSTANCE0 + i, in sdma_v4_4_2_sw_init()1498 AMDGPU_SDMA_IRQ_INSTANCE0 + i); in sdma_v4_4_2_hw_fini()2177 AMDGPU_SDMA_IRQ_INSTANCE0 + i); in sdma_v4_4_2_xcp_suspend()
859 (i == 0) ? AMDGPU_SDMA_IRQ_INSTANCE0 : in sdma_v2_4_sw_init()996 case AMDGPU_SDMA_IRQ_INSTANCE0: in sdma_v2_4_set_trap_irq_state()
970 (i == 0) ? AMDGPU_SDMA_IRQ_INSTANCE0 : in cik_sdma_sw_init()1105 case AMDGPU_SDMA_IRQ_INSTANCE0: in cik_sdma_set_trap_irq_state()
1425 (i == 0) ? AMDGPU_SDMA_IRQ_INSTANCE0 : in sdma_v5_0_sw_init()1590 u32 reg_offset = (type == AMDGPU_SDMA_IRQ_INSTANCE0) ? in sdma_v5_0_set_trap_irq_state()1900 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 + in sdma_v5_0_set_irq_funcs()
1145 (i == 0) ? AMDGPU_SDMA_IRQ_INSTANCE0 : in sdma_v3_0_sw_init()1332 case AMDGPU_SDMA_IRQ_INSTANCE0: in sdma_v3_0_set_trap_irq_state()
1872 AMDGPU_SDMA_IRQ_INSTANCE0 + i, in sdma_v4_0_sw_init()1910 AMDGPU_SDMA_IRQ_INSTANCE0 + i, in sdma_v4_0_sw_init()1978 AMDGPU_SDMA_IRQ_INSTANCE0 + i); in sdma_v4_0_hw_fini()
1325 AMDGPU_SDMA_IRQ_INSTANCE0 + i, in sdma_v6_0_sw_init()1678 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 + in sdma_v6_0_set_irq_funcs()
1313 AMDGPU_SDMA_IRQ_INSTANCE0 + i, in sdma_v7_0_sw_init()1666 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 + in sdma_v7_0_set_irq_funcs()
1303 AMDGPU_SDMA_IRQ_INSTANCE0 + i, in sdma_v5_2_sw_init()1860 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 + in sdma_v5_2_set_irq_funcs()