Searched refs:AMDGPU_MAX_MES_PIPES (Results 1 – 4 of 4) sorted by relevance
62 AMDGPU_MAX_MES_PIPES = 2, enumerator79 uint32_t fw_version[AMDGPU_MAX_MES_PIPES];88 struct amdgpu_ring ring[AMDGPU_MAX_MES_PIPES];89 spinlock_t ring_lock[AMDGPU_MAX_MES_PIPES];91 const struct firmware *fw[AMDGPU_MAX_MES_PIPES];94 struct amdgpu_bo *ucode_fw_obj[AMDGPU_MAX_MES_PIPES];95 uint64_t ucode_fw_gpu_addr[AMDGPU_MAX_MES_PIPES];96 uint32_t *ucode_fw_ptr[AMDGPU_MAX_MES_PIPES];97 uint64_t uc_start_addr[AMDGPU_MAX_MES_PIPES];100 struct amdgpu_bo *data_fw_obj[AMDGPU_MAX_MES_PIPES];[all …]
988 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { in mes_v12_0_enable()1058 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { in mes_v12_0_set_ucode_start_addr()1505 (AMDGPU_MAX_MES_PIPES * (AMDGPU_MES_LOG_BUFFER_SIZE + AMDGPU_MES_MSCRATCH_SIZE)) : in mes_v12_0_sw_init()1511 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { in mes_v12_0_sw_init()1536 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { in mes_v12_0_sw_fini()1798 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { in mes_v12_0_early_init()
905 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { in mes_v11_0_get_fw_version()943 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { in mes_v11_0_enable()1404 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { in mes_v11_0_sw_init()1435 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { in mes_v11_0_sw_fini()1693 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { in mes_v11_0_early_init()
140 for (i = 0; i < AMDGPU_MAX_MES_PIPES; i++) in amdgpu_mes_init()168 for (i = 0; i < AMDGPU_MAX_MES_PIPES; i++) { in amdgpu_mes_init()208 for (i = 0; i < AMDGPU_MAX_MES_PIPES; i++) { in amdgpu_mes_init()232 for (i = 0; i < AMDGPU_MAX_MES_PIPES; i++) { in amdgpu_mes_fini()