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Searched refs:AMDGPU_GPU_PAGE_ALIGN (Results 1 – 11 of 11) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_gart.h38 #define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK) macro
H A Damdgpu_uvd.h37 …(AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(((const struct common_firmware_header *)(adev)->uvd.fw->data)->…
H A Dvcn_v5_0_1.c445 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); in vcn_v5_0_1_mc_resume()
490 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn5_fw_shared))); in vcn_v5_0_1_mc_resume()
510 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); in vcn_v5_0_1_mc_resume_dpg_mode()
600 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn5_fw_shared)), 0, indirect); in vcn_v5_0_1_mc_resume_dpg_mode()
850 cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[i].fw->size + 4); in vcn_v5_0_1_start_sriov()
927 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared))); in vcn_v5_0_1_start_sriov()
H A Dvcn_v4_0_3.c494 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); in vcn_v4_0_3_mc_resume()
551 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared))); in vcn_v4_0_3_mc_resume()
571 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); in vcn_v4_0_3_mc_resume_dpg_mode()
661 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)), 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
1079 cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[i].fw->size + 4); in vcn_v4_0_3_start_sriov()
1156 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared))); in vcn_v4_0_3_start_sriov()
H A Dvcn_v5_0_0.c370 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); in vcn_v5_0_0_mc_resume()
413 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn5_fw_shared))); in vcn_v5_0_0_mc_resume()
433 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); in vcn_v5_0_0_mc_resume_dpg_mode()
519 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn5_fw_shared)), 0, indirect); in vcn_v5_0_0_mc_resume_dpg_mode()
H A Dvcn_v4_0.c455 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); in vcn_v4_0_mc_resume()
498 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared))); in vcn_v4_0_mc_resume()
517 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); in vcn_v4_0_mc_resume_dpg_mode()
603 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)), 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
1390 cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[i].fw->size + 4); in vcn_v4_0_start_sriov()
1489 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared))); in vcn_v4_0_start_sriov()
H A Dvcn_v2_0.c384 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[0].fw->size + 4); in vcn_v2_0_mc_resume()
433 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared))); in vcn_v2_0_mc_resume()
442 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[0].fw->size + 4); in vcn_v2_0_mc_resume_dpg_mode()
529 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
1984 size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[0].fw->size + 4); in vcn_v2_0_start_sriov()
H A Dvcn_v3_0.c524 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[inst].fw->size + 4); in vcn_v3_0_mc_resume()
569 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared))); in vcn_v3_0_mc_resume()
577 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[inst_idx].fw->size + 4); in vcn_v3_0_mc_resume_dpg_mode()
664 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
1435 cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[i].fw->size + 4); in vcn_v3_0_start_sriov()
H A Damdgpu_mes.h503 #define AMDGPU_MQD_SIZE_ALIGN(mqd_size) AMDGPU_GPU_PAGE_ALIGN(((mqd_size) + 32))
H A Damdgpu_vce.c491 addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg.gpu_addr); in amdgpu_vce_get_create_msg()
H A Damdgpu_uvd.c321 bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); in amdgpu_uvd_sw_init()