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Searched refs:ADF_CSR_WR (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/crypto/intel/qat/qat_common/
H A Dadf_gen2_hw_csr_data.h40 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
47 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
49 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
54 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
57 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
60 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
64 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
66 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
70 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
73 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
[all …]
H A Dadf_gen4_hw_csr_data.h73 ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
81 ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
93 ADF_CSR_WR((_csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
96 ADF_CSR_WR((_csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
121 ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
125 ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
132 ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
139 ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
146 ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
150 ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
[all …]
H A Dadf_gen4_pfvf.c43 ADF_CSR_WR(pmisc_addr, ADF_4XXX_VM2PF_MSK, val); in adf_gen4_enable_vf2pf_interrupts()
48 ADF_CSR_WR(pmisc_addr, ADF_4XXX_VM2PF_MSK, ADF_GEN4_VF_MSK); in adf_gen4_disable_all_vf2pf_interrupts()
75 ADF_CSR_WR(pmisc_addr, ADF_4XXX_VM2PF_MSK, ADF_GEN4_VF_MSK); in adf_gen4_disable_pending_vf2pf_interrupts()
76 ADF_CSR_WR(pmisc_addr, ADF_4XXX_VM2PF_MSK, disabled | sources); in adf_gen4_disable_pending_vf2pf_interrupts()
96 ADF_CSR_WR(pmisc_addr, pfvf_offset, csr_val | ADF_PFVF_INT); in adf_gen4_pfvf_send()
128 ADF_CSR_WR(pmisc_addr, pfvf_offset, csr_val & ~ADF_PFVF_INT); in adf_gen4_pfvf_recv()
H A Dadf_gen4_pm.c50 ADF_CSR_WR(pmisc, ADF_GEN4_PM_HOST_MSG, msg); in send_host_msg()
88 ADF_CSR_WR(pmisc, ADF_GEN4_PM_INTERRUPT, pm_int_sts); in pm_bh_handler()
93 ADF_CSR_WR(pmisc, ADF_GEN4_ERRMSK2, val); in pm_bh_handler()
118 ADF_CSR_WR(pmisc, ADF_GEN4_ERRMSK2, val); in adf_gen4_handle_pm_interrupt()
155 ADF_CSR_WR(pmisc, ADF_GEN4_PM_INTERRUPT, val); in adf_gen4_enable_pm()
160 ADF_CSR_WR(pmisc, ADF_GEN4_ERRMSK2, val); in adf_gen4_enable_pm()
H A Dicp_qat_hal.h126 ADF_CSR_WR((handle)->hal_cap_g_ctl_csr_addr_v, csr, val)
133 ADF_CSR_WR(AE_CSR_ADDR(handle, ae, csr), 0, val)
140 ADF_CSR_WR(AE_XFER_ADDR(handle, ae, reg), 0, val)
142 ADF_CSR_WR((handle)->hal_sram_addr_v, addr, val)
H A Dadf_gen2_pfvf.c60 ADF_CSR_WR(pmisc_addr, ADF_GEN2_ERRMSK3, val); in adf_gen2_enable_vf2pf_interrupts()
69 ADF_CSR_WR(pmisc_addr, ADF_GEN2_ERRMSK3, val); in adf_gen2_disable_all_vf2pf_interrupts()
101 ADF_CSR_WR(pmisc_addr, ADF_GEN2_ERRMSK3, errmsk3); in adf_gen2_disable_pending_vf2pf_interrupts()
106 ADF_CSR_WR(pmisc_addr, ADF_GEN2_ERRMSK3, errmsk3); in adf_gen2_disable_pending_vf2pf_interrupts()
224 ADF_CSR_WR(pmisc_addr, pfvf_offset, csr_msg | int_bit); in adf_gen2_pfvf_send()
255 ADF_CSR_WR(pmisc_addr, pfvf_offset, csr_val); in adf_gen2_pfvf_send()
319 ADF_CSR_WR(pmisc_addr, pfvf_offset, csr_val); in adf_gen2_pfvf_recv()
H A Dadf_vf_isr.c36 ADF_CSR_WR(pmisc_addr, ADF_VINTMSK_OFFSET, 0x0); in adf_enable_pf2vf_interrupts()
43 ADF_CSR_WR(pmisc_addr, ADF_VINTMSK_OFFSET, 0x2); in adf_disable_pf2vf_interrupts()
H A Dadf_rl.c275 ADF_CSR_WR(pmisc_addr, offset, node_id); in assign_rps_to_leaf()
290 ADF_CSR_WR(pmisc_addr, offset, parent_id); in assign_leaf_to_cluster()
304 ADF_CSR_WR(pmisc_addr, offset, parent_id); in assign_cluster_to_root()
1102 ADF_CSR_WR(pmisc_addr, rl_hw_data->pciin_tb_offset, in adf_rl_start()
1104 ADF_CSR_WR(pmisc_addr, rl_hw_data->pciout_tb_offset, in adf_rl_start()
H A Dadf_accel_devices.h364 #define ADF_CSR_WR(csr_base, csr_offset, val) \ macro
372 ADF_CSR_WR(csr_base, csr_low_offset, lower_32_bits(val)); \
373 ADF_CSR_WR(csr_base, csr_high_offset, upper_32_bits(val)); \
H A Dadf_gen4_vf_mig.c477 ADF_CSR_WR(csr, misc_states[i].ofs, regv); in adf_gen4_vfmig_load_misc()