Home
last modified time | relevance | path

Searched refs:ADF_CSR_RD (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/crypto/intel/qat/qat_common/
H A Dadf_gen4_hw_csr_data.h38 ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
42 ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
46 ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
49 ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
52 ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
55 ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
58 ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
61 ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
64 ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
67 ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
[all …]
H A Dadf_gen4_pm.c31 msg = ADF_CSR_RD(pmisc, ADF_GEN4_PM_HOST_MSG); in send_host_msg()
53 return read_poll_timeout(ADF_CSR_RD, msg, in send_host_msg()
91 val = ADF_CSR_RD(pmisc, ADF_GEN4_ERRMSK2); in pm_bh_handler()
107 errmsk2 = ADF_CSR_RD(pmisc, ADF_GEN4_ERRMSK2); in adf_gen4_handle_pm_interrupt()
111 errsou2 = ADF_CSR_RD(pmisc, ADF_GEN4_ERRSOU2); in adf_gen4_handle_pm_interrupt()
116 val = ADF_CSR_RD(pmisc, ADF_GEN4_ERRMSK2); in adf_gen4_handle_pm_interrupt()
120 val = ADF_CSR_RD(pmisc, ADF_GEN4_PM_INTERRUPT); in adf_gen4_handle_pm_interrupt()
150 val = ADF_CSR_RD(pmisc, ADF_GEN4_PM_INTERRUPT); in adf_gen4_enable_pm()
158 val = ADF_CSR_RD(pmisc, ADF_GEN4_ERRMSK2); in adf_gen4_enable_pm()
H A Dadf_gen4_pfvf.c42 val = ADF_CSR_RD(pmisc_addr, ADF_4XXX_VM2PF_MSK) & ~vf_mask; in adf_gen4_enable_vf2pf_interrupts()
56 sources = ADF_CSR_RD(pmisc_addr, ADF_4XXX_VM2PF_SOU); in adf_gen4_disable_pending_vf2pf_interrupts()
61 disabled = ADF_CSR_RD(pmisc_addr, ADF_4XXX_VM2PF_MSK); in adf_gen4_disable_pending_vf2pf_interrupts()
99 ret = read_poll_timeout(ADF_CSR_RD, csr_val, !(csr_val & ADF_PFVF_INT), in adf_gen4_pfvf_send()
118 csr_val = ADF_CSR_RD(pmisc_addr, pfvf_offset); in adf_gen4_pfvf_recv()
H A Dadf_gen2_pfvf.c58 u32 val = ADF_CSR_RD(pmisc_addr, ADF_GEN2_ERRMSK3) in adf_gen2_enable_vf2pf_interrupts()
67 u32 val = ADF_CSR_RD(pmisc_addr, ADF_GEN2_ERRMSK3) in adf_gen2_disable_all_vf2pf_interrupts()
78 errsou3 = ADF_CSR_RD(pmisc_addr, ADF_GEN2_ERRSOU3); in adf_gen2_disable_pending_vf2pf_interrupts()
85 errmsk3 = ADF_CSR_RD(pmisc_addr, ADF_GEN2_ERRMSK3); in adf_gen2_disable_pending_vf2pf_interrupts()
216 csr_val = ADF_CSR_RD(pmisc_addr, pfvf_offset); in adf_gen2_pfvf_send()
227 ret = read_poll_timeout(ADF_CSR_RD, csr_val, !(csr_val & int_bit), in adf_gen2_pfvf_send()
287 csr_val = ADF_CSR_RD(pmisc_addr, pfvf_offset); in adf_gen2_pfvf_recv()
H A Dadf_gen2_hw_csr_data.h31 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
34 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
37 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
H A Dicp_qat_hal.h128 ADF_CSR_RD((handle)->hal_cap_g_ctl_csr_addr_v, csr)
134 #define GET_AE_CSR(handle, ae, csr) ADF_CSR_RD(AE_CSR_ADDR(handle, ae, csr), 0)
H A Dadf_vf_isr.c144 v_int = ADF_CSR_RD(pmisc_bar_addr, ADF_VINTSOU_OFFSET); in adf_isr()
147 v_mask = ADF_CSR_RD(pmisc_bar_addr, ADF_VINTMSK_OFFSET); in adf_isr()
H A Dadf_accel_devices.h377 #define ADF_CSR_RD(csr_base, csr_offset) __raw_readl(csr_base + csr_offset) macro
H A Dadf_gen4_vf_mig.c711 regv = ADF_CSR_RD(csr, misc_states[i].offset); in adf_gen4_vfmig_save_misc()