Searched refs:AD7192_CLK_INT (Results 1 – 1 of 1) sorted by relevance
91 #define AD7192_CLK_INT 2 /* Internal 4.92 MHz Clock not */ macro454 st->mode |= AD7192_CLK_INT; in ad7192_clk_unprepare()460 st->clock_sel = AD7192_CLK_INT; in ad7192_clk_unprepare()536 st->clock_sel = AD7192_CLK_INT; in ad7192_clock_setup()