| /linux/lib/crypto/s390/ |
| H A D | chacha-s390.S | 465 #define A5 %v20 macro 504 VLR A5,K0 531 VAF A5,A5,B5 537 VX D5,D5,A5 569 VAF A5,A5,B5 575 VX D5,D5,A5 626 VAF A5,A5,B5 632 VX D5,D5,A5 664 VAF A5,A5,B5 670 VX D5,D5,A5 [all …]
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| /linux/arch/m68k/fpsp040/ |
| H A D | setox.S | 128 | p = R + R*R*(A1 + R*(A2 + R*(A3 + R*(A4 + R*A5)))) 130 | made as "short" as possible: A1 (which is 1/2), A4 and A5 138 | [ S*(A1 + S*(A3 + S*A5)) ] 513 |-- R + R*R*(A1 + R*(A2 + R*(A3 + R*(A4 + R*A5)))) 515 |--[R+R*S*(A2+S*A4)] + [S*(A1+S*(A3+S*A5))] 520 fmoves #0x3AB60B70,%fp2 | ...fp2 IS A5 523 fmulx %fp1,%fp2 | ...fp2 IS S*A5 527 faddd EXPA3,%fp2 | ...fp2 IS A3+S*A5 530 fmulx %fp1,%fp2 | ...fp2 IS S*(A3+S*A5) 538 fadds #0x3F000000,%fp2 | ...fp2 IS A1+S*(A3+S*A5) [all …]
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| H A D | slogn.S | 388 |--U + V*(A1+U*(A2+U*(A3+U*(A4+U*(A5+U*A6))))) WHICH IS 389 |--[U + V*(A1+V*(A3+V*A5))] + [U*V*(A2+V*(A4+V*A6))] 395 fmuld LOGA5,%fp2 | ...V*A5 398 faddd LOGA3,%fp2 | ...A3+V*A5 401 fmulx %fp3,%fp2 | ...V*(A3+V*A5) 404 faddd LOGA1,%fp2 | ...A1+V*(A3+V*A5) 408 fmulx %fp3,%fp2 | ...V*(A1+V*(A3+V*A5)), FP3 RELEASED 411 faddx %fp2,%fp0 | ...U+V*(A1+V*(A3+V*A5)), FP2 RELEASED
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| H A D | ssin.S | 257 faddd SINA5,%fp3 | ...A5+TA7 260 fmulx %fp1,%fp3 | ...T(A5+TA7) 263 faddd SINA3,%fp3 | ...A3+T(A5+TA7) 266 fmulx %fp3,%fp1 | ...T(A3+T(A5+TA7)) 269 faddx SINA1,%fp1 | ...A1+T(A3+T(A5+TA7)) 609 faddd SINA5,%fp1 | ...A5+S(A6+SA7) 614 fmulx %fp0,%fp1 | ...S(A5+S(A6+SA7)) 618 faddd SINA4,%fp1 | ...A4+S(A5+S(A6+SA7)) 682 faddd SINA5,%fp2 | ...A5+S(A6+SA7) 685 fmulx %fp0,%fp2 | ...S(A5+S(A6+SA7)) [all …]
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| H A D | binstr.S | 35 | A5. Add using the carry the 64-bit quantities in d2:d3 and d4:d5 102 | A5. Add mul by 8 to mul by 2. D1 contains the digit formed.
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| H A D | stwotox.S | 62 | P = r + r*r*(A1+r*(A2+...+r*A5)).
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| H A D | bindec.S | 39 | A5. Set ICTR = 0; 269 | A5. Set ICTR = 0;
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| H A D | decbin.S | 56 | A5. Form the final binary number by scaling the mantissa by
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| /linux/Documentation/arch/arm/ |
| H A D | microchip.rst | 101 * ARM Cortex-A5 based SoCs 112 …http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-11121-32-bit-Cortex-A5-Microcontroller-SAMA5… 114 * ARM Cortex-A5 + NEON based SoCs
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| /linux/arch/arm/mach-versatile/ |
| H A D | Kconfig | 259 - LogicTile Express 13MG (V2F-2XV6) with A5, A7, A9 or A15 SMMs 270 bool "Enable A5 and A9 only errata work-arounds" 277 based on Cortex-A5 and Cortex-A9 processors. In order to
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| /linux/Documentation/admin-guide/media/ |
| H A D | cx231xx-cardlist.rst | 30 - 0572:58A5
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| /linux/arch/arm64/boot/dts/amd/ |
| H A D | amd-seattle-xgbe-b.dtsi | 26 mac-address = [ 02 A1 A2 A3 A4 A5 ];
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| /linux/tools/perf/pmu-events/arch/x86/ |
| H A D | mapfile.csv | 35 GenuineIntel-6-(4E|5E|8E|9E|A5|A6),v59,skylake,core
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| /linux/arch/arm/boot/dts/arm/ |
| H A D | vexpress-v2p-ca5s.dts | 6 * Cortex-A5 MPCore (V2P-CA5s)
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| /linux/arch/m68k/ifpsp060/src/ |
| H A D | fplsp.S | 5102 fadd.d SINA5(%pc),%fp3 # A5+TA7 5105 fmul.x %fp1,%fp3 # T(A5+TA7) 5108 fadd.d SINA3(%pc),%fp3 # A3+T(A5+TA7) 5111 fmul.x %fp3,%fp1 # T(A3+T(A5+TA7)) 5114 fadd.x SINA1(%pc),%fp1 # A1+T(A3+T(A5+TA7)) 6785 # p = R + R*R*(A1 + R*(A2 + R*(A3 + R*(A4 + R*A5)))) # 6788 # and A5 are single precision; A2 and A3 are double # 6796 # [ S*(A1 + S*(A3 + S*A5)) ] # 7152 #-- R + R*R*(A1 + R*(A2 + R*(A3 + R*(A4 + R*A5)))) 7154 #--[R+R*S*(A2+S*A4)] + [S*(A1+S*(A3+S*A5))] [all …]
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| H A D | fpsp.S | 5184 #--R' + R'*S*( [A1+T(A3+T(A5+TA7))] + [S(A2+T(A4+TA6))]) 5223 fadd.x %fp2,%fp1 # [A1+T(A3+T(A5+TA7))]+[S(A2+T(A4+TA6))] 5418 fadd.d SINA5(%pc),%fp1 # A5+S(A6+SA7) 5421 fmul.x %fp0,%fp1 # S(A5+S(A6+SA7)) 5425 fadd.d SINA4(%pc),%fp1 # A4+S(A5+S(A6+SA7)) 5493 fadd.d SINA5(%pc),%fp2 # A5+S(A6+SA7) 5496 fmul.x %fp0,%fp2 # S(A5+S(A6+SA7)) 5499 fadd.d SINA4(%pc),%fp2 # A4+S(A5+S(A6+SA7)) 7019 # p = R+R*R*(A1+R*(A2+R*(A3+R*(A4+R*(A5+R*A6))))) # 7021 # are made as "short" as possible: A1 (which is 1/2), A5 # [all …]
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| /linux/arch/arm64/boot/dts/ti/ |
| H A D | k3-am62l3-evm.dts | 293 … AM62LX_IOPAD(0x0248, PIN_INPUT | PIN_DS_PULLUD_ENABLE | PIN_DS_PULL_UP, 0) /* (A5) USB1_DRVVBUS */
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| /linux/arch/arm/boot/dts/aspeed/ |
| H A D | aspeed-bmc-tyan-s8036.dts | 403 /*A5*/ "",
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| H A D | aspeed-bmc-tyan-s7106.dts | 449 /*A5*/ "",
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| /linux/arch/arm64/boot/dts/qcom/ |
| H A D | msm8916-samsung-a2015-common.dtsi | 87 * NOTE: A5 connects GPIO 76 to a reglator powering the motor
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| /linux/Documentation/driver-api/ |
| H A D | pin-control.rst | 436 In this 8x8 BGA package the pins { A8, A7, A6, A5 } can be used as an SPI port 438 some general-purpose GPIO pin. However, in another setting, pins { A5, B5 } can 483 function i2c is associated with the pins { A5, B5 }, enumerated as 486 The Function spi is associated with pin groups { A8, A7, A6, A5 }
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| /linux/drivers/pinctrl/renesas/ |
| H A D | pfc-r8a77970.c | 168 #define IP0_23_20 FM(DU_DR7) FM(MSIOF3_TXD) F_(0, 0) FM(A5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0… 414 PINMUX_IPSR_GPSR(IP0_23_20, A5),
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| H A D | pfc-r8a77980.c | 202 #define IP0_23_20 FM(DU_DR7) F_(0, 0) FM(GETHER_RMII_TXD0) FM(A5) F_(0, 0) F_(0, 0) F_(0, 0) F_… 487 PINMUX_IPSR_GPSR(IP0_23_20, A5),
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| H A D | pfc-r8a77990.c | 105 #define GPSR1_5 F_(A5, IP3_19_16) 242 #define IP3_19_16 FM(A5) FM(SCK4_A) FM(MSIOF3_SCK_B) FM(VI4_DATA9) FM(PWM3_B) F_(0, 0) FM(RIF2… 701 PINMUX_IPSR_GPSR(IP3_19_16, A5),
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| H A D | pfc-sh7734.c | 615 PINMUX_IPSR_GPSR(IP0_11_10, A5), 1373 GPIO_FN(A5), GPIO_FN(ST0_D1), GPIO_FN(LCD_DATA5_A),
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