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Searched refs:base_addr (Results 1 – 25 of 397) sorted by relevance

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/linux/drivers/w1/masters/
H A Damd_axi_w1.c60 void __iomem *base_addr; member
81 iowrite32(IRQ, amd_axi_w1_local->base_addr + AXIW1_IRQE_REG); in amd_axi_w1_wait_irq_interruptible_timeout()
114 while ((ioread32(amd_axi_w1_local->base_addr + AXIW1_STAT_REG) & AXIW1_READY) == 0) { in amd_axi_w1_touch_bit()
123 iowrite32(AXIW1_READBIT, amd_axi_w1_local->base_addr + AXIW1_INST_REG); in amd_axi_w1_touch_bit()
127 amd_axi_w1_local->base_addr + AXIW1_INST_REG); in amd_axi_w1_touch_bit()
130 iowrite32(AXIW1_GO, amd_axi_w1_local->base_addr + AXIW1_CTRL_REG); in amd_axi_w1_touch_bit()
133 while ((ioread32(amd_axi_w1_local->base_addr + AXIW1_STAT_REG) & AXIW1_DONE) != 1) { in amd_axi_w1_touch_bit()
141 val = (u8)(ioread32(amd_axi_w1_local->base_addr + AXIW1_DATA_REG) & AXIW1_READDATA); in amd_axi_w1_touch_bit()
144 iowrite32(AXI_CLEAR, amd_axi_w1_local->base_addr + AXIW1_CTRL_REG); in amd_axi_w1_touch_bit()
162 while ((ioread32(amd_axi_w1_local->base_addr + AXIW1_STAT_REG) & AXIW1_READY) == 0) { in amd_axi_w1_read_byte()
[all …]
/linux/include/trace/events/
H A Dpercpu.h15 size_t align, void *base_addr, int off,
18 TP_ARGS(call_site, reserved, is_atomic, size, align, base_addr, off,
27 __field( void *, base_addr )
39 __entry->base_addr = base_addr;
50 __entry->base_addr, __entry->off, __entry->ptr,
56 TP_PROTO(void *base_addr, int off, void __percpu *ptr),
58 TP_ARGS(base_addr, off, ptr),
61 __field( void *, base_addr )
67 __entry->base_addr = base_addr;
73 __entry->base_addr, __entry->off, __entry->ptr)
[all …]
/linux/drivers/irqchip/
H A Dirq-ftintc010.c26 #define FT010_IRQ_SOURCE(base_addr) (base_addr + 0x00) argument
27 #define FT010_IRQ_MASK(base_addr) (base_addr + 0x04) argument
28 #define FT010_IRQ_CLEAR(base_addr) (base_addr + 0x08) argument
30 #define FT010_IRQ_MODE(base_addr) (base_addr + 0x0C) argument
32 #define FT010_IRQ_POLARITY(base_addr) (base_addr + 0x10) argument
33 #define FT010_IRQ_STATUS(base_addr) (base_addr + 0x14) argument
34 #define FT010_FIQ_SOURCE(base_addr) (base_addr + 0x20) argument
35 #define FT010_FIQ_MASK(base_addr) (base_addr + 0x24) argument
36 #define FT010_FIQ_CLEAR(base_addr) (base_addr + 0x28) argument
37 #define FT010_FIQ_MODE(base_addr) (base_addr + 0x2C) argument
[all …]
/linux/drivers/char/ipmi/
H A Dipmi_dmi.c35 static void __init dmi_add_platform_ipmi(unsigned long base_addr, in dmi_add_platform_ipmi() argument
70 p.addr = base_addr; in dmi_add_platform_ipmi()
83 info->addr = base_addr; in dmi_add_platform_ipmi()
101 unsigned long base_addr) in ipmi_dmi_get_slave_addr() argument
108 info->addr == base_addr) in ipmi_dmi_get_slave_addr()
130 unsigned long base_addr; in dmi_decode_ipmi() local
142 memcpy(&base_addr, data + DMI_IPMI_ADDR, sizeof(unsigned long)); in dmi_decode_ipmi()
143 if (!base_addr) { in dmi_decode_ipmi()
150 base_addr = data[DMI_IPMI_ADDR] >> 1; in dmi_decode_ipmi()
151 if (base_addr == 0) { in dmi_decode_ipmi()
[all …]
/linux/drivers/parisc/
H A Ddino.c177 void __iomem *base_addr = d->hba.base_addr; in dino_cfg_read() local
180 DBG("%s: %p, %d, %d, %d\n", __func__, base_addr, devfn, where, in dino_cfg_read()
185 __raw_writel(v, base_addr + DINO_PCI_ADDR); in dino_cfg_read()
189 *val = readb(base_addr + DINO_CONFIG_DATA + (where & 3)); in dino_cfg_read()
191 *val = readw(base_addr + DINO_CONFIG_DATA + (where & 2)); in dino_cfg_read()
193 *val = readl(base_addr + DINO_CONFIG_DATA); in dino_cfg_read()
212 void __iomem *base_addr = d->hba.base_addr; in dino_cfg_write() local
215 DBG("%s: %p, %d, %d, %d\n", __func__, base_addr, devfn, where, in dino_cfg_write()
220 __raw_writel(v & 0xffffff00, base_addr + DINO_PCI_ADDR); in dino_cfg_write()
221 __raw_readl(base_addr + DINO_CONFIG_DATA); in dino_cfg_write()
[all …]
H A Dlba_pci.c207 error_config = READ_REG32(d->hba.base_addr + LBA_ERROR_CONFIG); \
210 status_control = READ_REG32(d->hba.base_addr + LBA_STAT_CTL); \
216 arb_mask = READ_REG32(d->hba.base_addr + LBA_ARB_MASK); \
222 WRITE_REG32(0x1, d->hba.base_addr + LBA_ARB_MASK); \
228 WRITE_REG32(error_config | LBA_SMART_MODE, d->hba.base_addr + LBA_ERROR_CONFIG); \
237 WRITE_REG32(tok | PCI_VENDOR_ID, (d)->hba.base_addr + LBA_PCI_CFG_ADDR);\
242 lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
247 WRITE_REG32(~0, (d)->hba.base_addr + LBA_PCI_CFG_DATA); \
252 lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
307 WRITE_REG32(((addr) & ~3), (d)->hba.base_addr + LBA_PCI_CFG_ADDR);
[all …]
/linux/drivers/gpio/
H A Dgpio-zynq.c128 void __iomem *base_addr; member
236 data = readl_relaxed(gpio->base_addr + in zynq_gpio_get_value()
239 data = readl_relaxed(gpio->base_addr + in zynq_gpio_get_value()
244 data = readl_relaxed(gpio->base_addr + in zynq_gpio_get_value()
247 data = readl_relaxed(gpio->base_addr + in zynq_gpio_get_value()
252 data = readl_relaxed(gpio->base_addr + in zynq_gpio_get_value()
292 writel_relaxed(state, gpio->base_addr + reg_offset); in zynq_gpio_set_value()
324 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); in zynq_gpio_dir_in()
326 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); in zynq_gpio_dir_in()
356 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); in zynq_gpio_dir_out()
[all …]
H A Dgpio-ts4800.c22 void __iomem *base_addr; in ts4800_gpio_probe() local
30 base_addr = devm_platform_ioremap_resource(pdev, 0); in ts4800_gpio_probe()
31 if (IS_ERR(base_addr)) in ts4800_gpio_probe()
32 return PTR_ERR(base_addr); in ts4800_gpio_probe()
44 retval = bgpio_init(chip, &pdev->dev, 2, base_addr + INPUT_REG_OFFSET, in ts4800_gpio_probe()
45 base_addr + OUTPUT_REG_OFFSET, NULL, in ts4800_gpio_probe()
46 base_addr + DIRECTION_REG_OFFSET, NULL, 0); in ts4800_gpio_probe()
/linux/drivers/net/ethernet/ti/
H A Dtlan.c337 outl(TLAN_HC_AD_RST, dev->base_addr + TLAN_HOST_CMD); in tlan_stop()
504 dev->base_addr = pci_io_base; in tlan_probe1()
521 dev->base_addr = ioaddr; in tlan_probe1()
579 (int)dev->base_addr, in tlan_probe1()
614 release_region(dev->base_addr, 0x10); in tlan_eisa_cleanup()
897 priv->tlan_rev = tlan_dio_read8(dev->base_addr, TLAN_DEF_REVISION); in tlan_open()
1086 outl(tail_list_phys, dev->base_addr + TLAN_CH_PARM); in tlan_start_tx()
1087 outl(TLAN_HC_GO, dev->base_addr + TLAN_HOST_CMD); in tlan_start_tx()
1140 host_int = inw(dev->base_addr + TLAN_HOST_INT); in tlan_handle_interrupt()
1146 outw(host_int, dev->base_addr + TLAN_HOST_INT); in tlan_handle_interrupt()
[all …]
H A Dtlan.h444 static inline u8 tlan_dio_read8(u16 base_addr, u16 internal_addr) in tlan_dio_read8() argument
446 outw(internal_addr, base_addr + TLAN_DIO_ADR); in tlan_dio_read8()
447 return inb((base_addr + TLAN_DIO_DATA) + (internal_addr & 0x3)); in tlan_dio_read8()
454 static inline u16 tlan_dio_read16(u16 base_addr, u16 internal_addr) in tlan_dio_read16() argument
456 outw(internal_addr, base_addr + TLAN_DIO_ADR); in tlan_dio_read16()
457 return inw((base_addr + TLAN_DIO_DATA) + (internal_addr & 0x2)); in tlan_dio_read16()
464 static inline u32 tlan_dio_read32(u16 base_addr, u16 internal_addr) in tlan_dio_read32() argument
466 outw(internal_addr, base_addr + TLAN_DIO_ADR); in tlan_dio_read32()
467 return inl(base_addr + TLAN_DIO_DATA); in tlan_dio_read32()
474 static inline void tlan_dio_write8(u16 base_addr, u16 internal_addr, u8 data) in tlan_dio_write8() argument
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/linux/drivers/net/ethernet/8390/
H A Dsmc-ultra.c142 int base_addr = dev->base_addr; in do_ultra_probe() local
145 if (base_addr > 0x1ff) /* Check a single specified location. */ in do_ultra_probe()
146 return ultra_probe1(dev, base_addr); in do_ultra_probe()
147 else if (base_addr != 0) /* Don't probe at all. */ in do_ultra_probe()
279 dev->base_addr = ioaddr+ULTRA_NIC_OFFSET; in ultra_probe1()
361 dev->base_addr = pnp_port_start(idev, 0); in ultra_probe_isapnp()
366 dev->base_addr, dev->irq); in ultra_probe_isapnp()
367 if (ultra_probe1(dev, dev->base_addr) != 0) { /* Shouldn't happen. */ in ultra_probe_isapnp()
370 dev->base_addr); in ultra_probe_isapnp()
390 int ioaddr = dev->base_addr - ULTRA_NIC_OFFSET; /* ASIC addr */ in ultra_open()
[all …]
/linux/drivers/clocksource/
H A Dtimer-cadence-ttc.c75 void __iomem *base_addr; member
116 ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET); in ttc_set_interval()
118 writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET); in ttc_set_interval()
120 writel_relaxed(cycles, timer->base_addr + TTC_INTR_VAL_OFFSET); in ttc_set_interval()
128 writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET); in ttc_set_interval()
145 readl_relaxed(timer->base_addr + TTC_ISR_OFFSET); in ttc_clock_event_interrupt()
162 return (u64)readl_relaxed(timer->base_addr + in __ttc_clocksource_read()
203 ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET); in ttc_shutdown()
205 writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET); in ttc_shutdown()
231 ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET); in ttc_resume()
[all …]
/linux/drivers/net/hamradio/
H A Dbaycom_ser_hdx.c158 outb(0x81, LCR(dev->base_addr)); /* DLAB = 1 */ in ser12_set_divisor()
159 outb(divisor, DLL(dev->base_addr)); in ser12_set_divisor()
160 outb(0, DLM(dev->base_addr)); in ser12_set_divisor()
161 outb(0x01, LCR(dev->base_addr)); /* word length = 6 */ in ser12_set_divisor()
167 outb(0x00, THR(dev->base_addr)); in ser12_set_divisor()
193 outb(0x0e | (!!bc->modem.ser12.tx_bit), MCR(dev->base_addr)); in ser12_tx()
209 cur_s = inb(MSR(dev->base_addr)) & 0x10; /* the CTS line */ in ser12_rx()
339 outb(0x0d, MCR(dev->base_addr)); /* transmitter off */ in ser12_rx()
346 hdlcdrv_setdcd(&bc->hdrv, !((inb(MSR(dev->base_addr)) ^ bc->opt_dcd) & 0x80)); in ser12_rx()
371 if ((iir = inb(IIR(dev->base_addr))) & 1) in ser12_interrupt()
[all …]
H A Dyam.c465 outb(0, IER(dev->base_addr)); in yam_set_uart()
466 outb(LCR_DLAB | LCR_BIT8, LCR(dev->base_addr)); in yam_set_uart()
467 outb(divisor, DLL(dev->base_addr)); in yam_set_uart()
468 outb(0, DLM(dev->base_addr)); in yam_set_uart()
469 outb(LCR_BIT8, LCR(dev->base_addr)); in yam_set_uart()
470 outb(PTT_OFF, MCR(dev->base_addr)); in yam_set_uart()
471 outb(0x00, FCR(dev->base_addr)); in yam_set_uart()
475 inb(RBR(dev->base_addr)); in yam_set_uart()
476 inb(MSR(dev->base_addr)); in yam_set_uart()
480 outb(ENABLE_RTXINT, IER(dev->base_addr)); in yam_set_uart()
[all …]
/linux/tools/testing/selftests/mm/
H A Dmap_fixed_noreplace.c43 unsigned long base_addr; in main() local
54 base_addr = find_base_addr(size); in main()
59 addr = base_addr; in main()
73 addr = base_addr + page_size; in main()
91 addr = base_addr; in main()
110 addr = base_addr + (2 * page_size); in main()
128 addr = base_addr + (3 * page_size); in main()
146 addr = base_addr; in main()
164 addr = base_addr; in main()
182 addr = base_addr in main()
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/linux/drivers/clk/mediatek/
H A Dclk-apmixed.c22 void __iomem *base_addr; member
34 return (readl(tx->base_addr) & REF2USB_EN_MASK) == REF2USB_EN_MASK; in mtk_ref2usb_tx_is_prepared()
42 val = readl(tx->base_addr); in mtk_ref2usb_tx_prepare()
45 writel(val, tx->base_addr); in mtk_ref2usb_tx_prepare()
49 writel(val, tx->base_addr); in mtk_ref2usb_tx_prepare()
52 writel(val, tx->base_addr); in mtk_ref2usb_tx_prepare()
62 val = readl(tx->base_addr); in mtk_ref2usb_tx_unprepare()
64 writel(val, tx->base_addr); in mtk_ref2usb_tx_unprepare()
84 tx->base_addr = reg; in mtk_clk_register_ref2usb_tx()
/linux/drivers/net/wwan/t7xx/
H A Dt7xx_mhccif.c34 void __iomem *mhccif_pbase = t7xx_dev->base_addr.mhccif_rc_base; in t7xx_mhccif_clear_interrupts()
82 return ioread32(t7xx_dev->base_addr.mhccif_rc_base + REG_EP2RC_SW_INT_STS); in t7xx_mhccif_read_sw_int_sts()
87 iowrite32(val, t7xx_dev->base_addr.mhccif_rc_base + REG_EP2RC_SW_INT_EAP_MASK_SET); in t7xx_mhccif_mask_set()
92 iowrite32(val, t7xx_dev->base_addr.mhccif_rc_base + REG_EP2RC_SW_INT_EAP_MASK_CLR); in t7xx_mhccif_mask_clr()
97 return ioread32(t7xx_dev->base_addr.mhccif_rc_base + REG_EP2RC_SW_INT_EAP_MASK); in t7xx_mhccif_mask_get()
107 t7xx_dev->base_addr.mhccif_rc_base = t7xx_dev->base_addr.pcie_ext_reg_base + in t7xx_mhccif_init()
109 t7xx_dev->base_addr.pcie_dev_reg_trsl_addr; in t7xx_mhccif_init()
118 void __iomem *mhccif_pbase = t7xx_dev->base_addr.mhccif_rc_base; in t7xx_mhccif_h2d_swint_trigger()
/linux/drivers/net/arcnet/
H A Dcom90io.c73 int ioaddr = dev->base_addr; in get_buffer_byte()
85 int ioaddr = dev->base_addr; in put_buffer_byte()
98 int ioaddr = dev->base_addr; in get_whole_buffer()
114 int ioaddr = dev->base_addr; in put_whole_buffer()
132 int ioaddr = dev->base_addr, status; in com90io_probe()
224 int ioaddr = dev->base_addr; in com90io_found()
234 if (!request_region(dev->base_addr, ARCNET_TOTAL_SIZE, in com90io_found()
262 release_region(dev->base_addr, ARCNET_TOTAL_SIZE); in com90io_found()
267 dev->dev_addr[0], dev->base_addr, dev->irq); in com90io_found()
282 short ioaddr = dev->base_addr; in com90io_reset()
[all …]
/linux/arch/alpha/kernel/
H A Dsmc37c669.c1237 SMC37c669_SERIAL_BASE_ADDRESS_REGISTER base_addr; in SMC37c669_enable_device() local
1254 base_addr.as_uchar = 0; in SMC37c669_enable_device()
1255 base_addr.by_field.addr9_3 = local_config[ func ].port1 >> 3; in SMC37c669_enable_device()
1259 base_addr.as_uchar in SMC37c669_enable_device()
1266 SMC37c669_SERIAL_BASE_ADDRESS_REGISTER base_addr; in SMC37c669_enable_device() local
1283 base_addr.as_uchar = 0; in SMC37c669_enable_device()
1284 base_addr.by_field.addr9_3 = local_config[ func ].port1 >> 3; in SMC37c669_enable_device()
1288 base_addr.as_uchar in SMC37c669_enable_device()
1295 SMC37c669_PARALLEL_BASE_ADDRESS_REGISTER base_addr; in SMC37c669_enable_device() local
1331 base_addr.as_uchar = 0; in SMC37c669_enable_device()
[all …]
/linux/arch/m68k/mvme16x/
H A Dconfig.c204 volatile unsigned char *base_addr = (u_char *)CD2401_ADDR; in mvme16x_cons_write() local
213 base_addr[CyCAR] = (u_char)port; in mvme16x_cons_write()
214 while (base_addr[CyCCR]) in mvme16x_cons_write()
216 base_addr[CyCCR] = CyENB_XMTR; in mvme16x_cons_write()
218 ier = base_addr[CyIER]; in mvme16x_cons_write()
219 base_addr[CyIER] = CyTxMpty; in mvme16x_cons_write()
226 if ((base_addr[CyLICR] >> 2) == port) { in mvme16x_cons_write()
229 base_addr[CyTEOIR] = CyNOTRANS; in mvme16x_cons_write()
233 base_addr[CyTDR] = '\n'; in mvme16x_cons_write()
239 base_addr[CyTDR] = '\r'; in mvme16x_cons_write()
[all …]
/linux/arch/powerpc/include/asm/
H A Ddcr-native.h78 static inline unsigned __mfdcri(int base_addr, int base_data, int reg) in __mfdcri() argument
85 mtdcrx(base_addr, reg); in __mfdcri()
88 __mtdcr(base_addr, reg); in __mfdcri()
95 static inline void __mtdcri(int base_addr, int base_data, int reg, in __mtdcri() argument
102 mtdcrx(base_addr, reg); in __mtdcri()
105 __mtdcr(base_addr, reg); in __mtdcri()
111 static inline void __dcri_clrset(int base_addr, int base_data, int reg, in __dcri_clrset() argument
119 mtdcrx(base_addr, reg); in __dcri_clrset()
123 __mtdcr(base_addr, reg); in __dcri_clrset()
/linux/arch/sparc/prom/
H A Dmemory.c24 sp_banks[index].base_addr = (unsigned long) p->start_adr; in prom_meminit_v0()
43 sp_banks[i].base_addr = reg[i].phys_addr; in prom_meminit_v2()
54 if (x->base_addr > y->base_addr) in sp_banks_cmp()
56 if (x->base_addr < y->base_addr) in sp_banks_cmp()
83 sp_banks[num_ents].base_addr = 0xdeadbeef; in prom_meminit()
/linux/arch/sparc/mm/
H A Dinit_32.c64 unsigned long start_pfn = sp_banks[i].base_addr >> PAGE_SHIFT; in calc_highpages()
65 unsigned long end_pfn = (sp_banks[i].base_addr + sp_banks[i].num_bytes) >> PAGE_SHIFT; in calc_highpages()
85 last_pfn = (sp_banks[0].base_addr + sp_banks[0].num_bytes) >> PAGE_SHIFT; in calc_max_low_pfn()
87 curr_pfn = sp_banks[i].base_addr >> PAGE_SHIFT; in calc_max_low_pfn()
95 last_pfn = (sp_banks[i].base_addr + sp_banks[i].num_bytes) >> PAGE_SHIFT; in calc_max_low_pfn()
143 end_of_phys_memory = sp_banks[i].base_addr + in bootmem_init()
155 sp_banks[i].base_addr = 0xdeadbeef; in bootmem_init()
157 memblock_add(sp_banks[i].base_addr, in bootmem_init()
160 sp_banks[i+1].base_addr = 0xdeadbeef; in bootmem_init()
165 memblock_add(sp_banks[i].base_addr, sp_banks[i].num_bytes); in bootmem_init()
[all …]
/linux/drivers/gpu/drm/msm/disp/
H A Dmsm_disp_snapshot_util.c12 static void msm_disp_state_dump_regs(u32 **reg, u32 aligned_len, void __iomem *base_addr) in msm_disp_state_dump_regs() argument
25 addr = base_addr; in msm_disp_state_dump_regs()
26 end_addr = base_addr + aligned_len; in msm_disp_state_dump_regs()
49 void __iomem *base_addr, struct drm_printer *p) in msm_disp_state_print_regs() argument
60 addr = base_addr; in msm_disp_state_print_regs()
65 (unsigned long)(addr - base_addr), in msm_disp_state_print_regs()
90 msm_disp_state_print_regs(block->state, block->size, block->base_addr, p); in msm_disp_state_print()
170 void __iomem *base_addr, const char *fmt, ...) in msm_disp_snapshot_add_block() argument
190 new_blk->base_addr = base_addr; in msm_disp_snapshot_add_block()
192 msm_disp_state_dump_regs(&new_blk->state, new_blk->size, base_addr); in msm_disp_snapshot_add_block()
/linux/drivers/scsi/
H A D3w-sas.h176 ((unsigned char __iomem *)x->base_addr + TWL_STATUS)
178 ((unsigned char __iomem *)x->base_addr + TWL_HOBQPL)
180 ((unsigned char __iomem *)x->base_addr + TWL_HOBQPH)
182 ((unsigned char __iomem *)x->base_addr + TWL_HOBDB)
184 ((unsigned char __iomem *)x->base_addr + TWL_HOBDBC)
186 ((unsigned char __iomem *)x->base_addr + TWL_HIMASK)
188 ((unsigned char __iomem *)x->base_addr + TWL_HISTAT)
190 ((unsigned char __iomem *)x->base_addr + TWL_HIBQPH)
192 ((unsigned char __iomem *)x->base_addr + TWL_HIBQPL)
194 ((unsigned char __iomem *)x->base_addr + TWL_HIBDB)
[all …]

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