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/illumos-gate/usr/src/test/crypto-tests/tests/digest/data/
H A DREADME3 The SHA* vectors are taken directly from:
6 The MD5 vectors are taken from:
9 Given that the initial format of the MD5 vectors is different than the SHA data,
/illumos-gate/usr/src/uts/common/io/fibre-channel/fca/qlc/
H A Dqlc.conf257 msix-vectors=5;
/illumos-gate/usr/src/lib/librstp/common/
H A Dstp_in.h140 STP_IN_init (STP_VECTORS_T *vectors);
H A Dstp_in.c231 STP_IN_init (STP_VECTORS_T *vectors) in STP_IN_init() argument
234 stp_vectors = vectors; in STP_IN_init()
/illumos-gate/usr/src/common/bignum/i386/
H A Dbignum_i386_asm.S213 / r = a * digit, r and a are vectors of length len
447 / r = a * digit, r and a are vectors of length len
474 / r = r + a * digit, r and a are vectors of length len
879 / r = a * a, r and a are vectors of length len
/illumos-gate/usr/src/common/bignum/amd64/
H A Dbignum_amd64_asm.S230 / r += a * digit, r and a are vectors of length len
/illumos-gate/usr/src/lib/libc/port/stdio/
H A DREADME.design254 * All of the operations vectors must be implemented.
/illumos-gate/usr/src/uts/common/io/cxgbe/firmware/
H A Dt4fw_cfg.txt264 # For PF0-3 we assign 8 vectors each for NIC Ingress Queues of the associated
H A Dt5fw_cfg.txt299 # For PF0-3 we assign 8 vectors each for NIC Ingress Queues of the associated
H A Dt6fw_cfg.txt316 # For PF0-3 we assign 8 vectors each for NIC Ingress Queues of the associated
/illumos-gate/usr/src/uts/common/io/qede/579xx/drivers/ecore/documentation/
H A Decore.tex945 As a result, when in CMT the MSI-X vectors are split between the two hw-func/Incomtions.
963 …\item Enable slowpath interrupts -- the first 2 MSI-X vectors should be used for slowpath. Notice …
969 …rtant to remember that there were 2 different DPCs allocated and 2 MSI-X vectors configured to sup…
1009 …CQ / CmdQ / RQ). \newline This should be $\leq$ number of available MSIX vectors for the PF \\ \hl…
1142 … queues (CQ / CmdQ / RQ). This should be $\leq$ number of available MSIX vectors for the PF \\ \hl…
1262 …make sure enough resources are available for this number (number of msix vectors and cnq resource\…
/illumos-gate/usr/src/uts/common/io/qede/579xx/drivers/ecore/
H A Drelease.txt4841 "Consecutive igu vectors for HWFN 0 vfs is broken".
/illumos-gate/usr/src/uts/intel/io/acpica/
H A Dchanges.txt3858 FACS table (Waking vectors and Global Lock)