1 /*
2 * This file and its contents are supplied under the terms of the
3 * Common Development and Distribution License ("CDDL"), version 1.0.
4 * You may only use this file in accordance with the terms of version
5 * 1.0 of the CDDL.
6 *
7 * A full copy of the text of the CDDL should have accompanied this
8 * source. A copy of the CDDL is also available via the Internet at
9 * http://www.illumos.org/license/CDDL.
10 */
11
12 /*
13 * This file is part of the Chelsio T4/T5/T6 Ethernet driver.
14 *
15 * Copyright (C) 2005-2019 Chelsio Communications. All rights reserved.
16 *
17 * This program is distributed in the hope that it will be useful, but WITHOUT
18 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
19 * FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this
20 * release for licensing terms and conditions.
21 */
22
23 /*
24 * Copyright 2020 RackTop Systems, Inc.
25 * Copyright 2023 Oxide Computer Company
26 */
27
28 #ifndef __CHELSIO_COMMON_H
29 #define __CHELSIO_COMMON_H
30
31 #include "t4_hw.h"
32 #include "t4_chip_type.h"
33
34 #define GLBL_INTR_MASK (F_CIM | F_MPS | F_PL | F_PCIE | F_MC0 | F_EDC0 | \
35 F_EDC1 | F_LE | F_TP | F_MA | F_PM_TX | F_PM_RX | F_ULP_RX | \
36 F_CPL_SWITCH | F_SGE | F_ULP_TX | F_SF)
37
38 #ifdef __cplusplus
39 extern "C" {
40 #endif
41
42 #ifndef __linux__
43 #define __force
44 #define usleep_range(_min, _max) msleep(_max / 1000)
45 #endif
46
47 /*
48 * Firmware minimum version macros are used by t4_check_fw_version() to check
49 * if the FW is supported by the driver.
50 * Initially these macros were in t4fw_interface.h, but was removed, as the
51 * file is automatically replaced during a new FW commit. So untill these
52 * macros moves to one of the firmware header files, it has to be here.
53 */
54 #define T4FW_MIN_VERSION_MAJOR 0x01
55 #define T4FW_MIN_VERSION_MINOR 0x04
56 #define T4FW_MIN_VERSION_MICRO 0x00
57
58 #define T5FW_MIN_VERSION_MAJOR 0x00
59 #define T5FW_MIN_VERSION_MINOR 0x00
60 #define T5FW_MIN_VERSION_MICRO 0x00
61
62 #define T6FW_MIN_VERSION_MAJOR 0x00
63 #define T6FW_MIN_VERSION_MINOR 0x00
64 #define T6FW_MIN_VERSION_MICRO 0x00
65
66 enum {
67 MAX_NPORTS = 4, /* max # of ports */
68 SERNUM_LEN = 24, /* Serial # length */
69 EC_LEN = 16, /* E/C length */
70 ID_LEN = 16, /* ID length */
71 PN_LEN = 16, /* Part Number length */
72 MACADDR_LEN = 12, /* MAC Address length */
73 };
74
75 enum {
76 T4_REGMAP_SIZE = (160 * 1024),
77 T5_REGMAP_SIZE = (332 * 1024),
78 };
79
80 enum { MEM_EDC0, MEM_EDC1, MEM_MC, MEM_MC0 = MEM_MC, MEM_MC1, MEM_HMA };
81
82 enum {
83 MEMWIN0_APERTURE = 2048,
84 MEMWIN0_BASE = 0x1b800,
85
86 MEMWIN1_APERTURE = 32768,
87 MEMWIN1_BASE = 0x28000,
88
89 MEMWIN2_APERTURE = 65536,
90 MEMWIN2_BASE = 0x30000,
91
92 MEMWIN2_APERTURE_T5 = 128 * 1024,
93 MEMWIN2_BASE_T5 = 0x60000,
94 };
95
96 enum dev_master { MASTER_CANT, MASTER_MAY, MASTER_MUST };
97
98 enum dev_state { DEV_STATE_UNINIT, DEV_STATE_INIT, DEV_STATE_ERR };
99
100 enum {
101 PAUSE_RX = 1 << 0,
102 PAUSE_TX = 1 << 1,
103 PAUSE_AUTONEG = 1 << 2
104 };
105 typedef unsigned char cc_pause_t;
106
107 enum {
108 FEC_RS = 1 << 0, /* Reed-Solomon */
109 FEC_BASER_RS = 1 << 1, /* Base-R, aka Firecode */
110 FEC_NONE = 1 << 2, /* no FEC */
111 FEC_FORCE = 1 << 3, /* Force specified FEC */
112
113 /*
114 * Pseudo FECs that translate to real FECs. The firmware knows nothing
115 * about these and they start at M_FW_PORT_CAP32_FEC + 1. AUTO should
116 * be set all by itself.
117 */
118 FEC_AUTO = 1 << 5,
119 };
120 typedef unsigned char cc_fec_t;
121
122 enum {
123 ULP_T10DIF_ISCSI = 1 << 0,
124 ULP_T10DIF_FCOE = 1 << 1
125 };
126
127 enum {
128 ULP_CRYPTO_LOOKASIDE = 1 << 0,
129 ULP_CRYPTO_INLINE_TLS = 1 << 1
130 };
131
132 struct port_stats {
133 u64 tx_octets; /* total # of octets in good frames */
134 u64 tx_frames; /* all good frames */
135 u64 tx_bcast_frames; /* all broadcast frames */
136 u64 tx_mcast_frames; /* all multicast frames */
137 u64 tx_ucast_frames; /* all unicast frames */
138 u64 tx_error_frames; /* all error frames */
139
140 u64 tx_frames_64; /* # of Tx frames in a particular range */
141 u64 tx_frames_65_127;
142 u64 tx_frames_128_255;
143 u64 tx_frames_256_511;
144 u64 tx_frames_512_1023;
145 u64 tx_frames_1024_1518;
146 u64 tx_frames_1519_max;
147
148 u64 tx_drop; /* # of dropped Tx frames */
149 u64 tx_pause; /* # of transmitted pause frames */
150 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */
151 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */
152 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */
153 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */
154 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */
155 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */
156 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */
157 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */
158
159 u64 rx_octets; /* total # of octets in good frames */
160 u64 rx_frames; /* all good frames */
161 u64 rx_bcast_frames; /* all broadcast frames */
162 u64 rx_mcast_frames; /* all multicast frames */
163 u64 rx_ucast_frames; /* all unicast frames */
164 u64 rx_too_long; /* # of frames exceeding MTU */
165 u64 rx_jabber; /* # of jabber frames */
166 u64 rx_fcs_err; /* # of received frames with bad FCS */
167 u64 rx_len_err; /* # of received frames with length error */
168 u64 rx_symbol_err; /* symbol errors */
169 u64 rx_runt; /* # of short frames */
170
171 u64 rx_frames_64; /* # of Rx frames in a particular range */
172 u64 rx_frames_65_127;
173 u64 rx_frames_128_255;
174 u64 rx_frames_256_511;
175 u64 rx_frames_512_1023;
176 u64 rx_frames_1024_1518;
177 u64 rx_frames_1519_max;
178
179 u64 rx_pause; /* # of received pause frames */
180 u64 rx_ppp0; /* # of received PPP prio 0 frames */
181 u64 rx_ppp1; /* # of received PPP prio 1 frames */
182 u64 rx_ppp2; /* # of received PPP prio 2 frames */
183 u64 rx_ppp3; /* # of received PPP prio 3 frames */
184 u64 rx_ppp4; /* # of received PPP prio 4 frames */
185 u64 rx_ppp5; /* # of received PPP prio 5 frames */
186 u64 rx_ppp6; /* # of received PPP prio 6 frames */
187 u64 rx_ppp7; /* # of received PPP prio 7 frames */
188
189 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */
190 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */
191 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */
192 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */
193 u64 rx_trunc0; /* buffer-group 0 truncated packets */
194 u64 rx_trunc1; /* buffer-group 1 truncated packets */
195 u64 rx_trunc2; /* buffer-group 2 truncated packets */
196 u64 rx_trunc3; /* buffer-group 3 truncated packets */
197 };
198
199 struct lb_port_stats {
200 u64 octets;
201 u64 frames;
202 u64 bcast_frames;
203 u64 mcast_frames;
204 u64 ucast_frames;
205 u64 error_frames;
206
207 u64 frames_64;
208 u64 frames_65_127;
209 u64 frames_128_255;
210 u64 frames_256_511;
211 u64 frames_512_1023;
212 u64 frames_1024_1518;
213 u64 frames_1519_max;
214
215 u64 drop;
216
217 u64 ovflow0;
218 u64 ovflow1;
219 u64 ovflow2;
220 u64 ovflow3;
221 u64 trunc0;
222 u64 trunc1;
223 u64 trunc2;
224 u64 trunc3;
225 };
226
227 struct tp_tcp_stats {
228 u32 tcp_out_rsts;
229 u64 tcp_in_segs;
230 u64 tcp_out_segs;
231 u64 tcp_retrans_segs;
232 };
233
234 struct tp_usm_stats {
235 u32 frames;
236 u32 drops;
237 u64 octets;
238 };
239
240 struct tp_fcoe_stats {
241 u32 frames_ddp;
242 u32 frames_drop;
243 u64 octets_ddp;
244 };
245
246 struct tp_err_stats {
247 u32 mac_in_errs[4];
248 u32 hdr_in_errs[4];
249 u32 tcp_in_errs[4];
250 u32 tnl_cong_drops[4];
251 u32 ofld_chan_drops[4];
252 u32 tnl_tx_drops[4];
253 u32 ofld_vlan_drops[4];
254 u32 tcp6_in_errs[4];
255 u32 ofld_no_neigh;
256 u32 ofld_cong_defer;
257 };
258
259 struct tp_proxy_stats {
260 u32 proxy[4];
261 };
262
263 struct tp_cpl_stats {
264 u32 req[4];
265 u32 rsp[4];
266 };
267
268 struct tp_rdma_stats {
269 u32 rqe_dfr_pkt;
270 u32 rqe_dfr_mod;
271 };
272
273 struct sge_params {
274 u32 hps; /* host page size for our PF/VF */
275 u32 eq_qpp; /* egress queues/page for our PF/VF */
276 u32 iq_qpp; /* egress queues/page for our PF/VF */
277 };
278
279 struct tp_params {
280 unsigned int tre; /* log2 of core clocks per TP tick */
281 unsigned int dack_re; /* DACK timer resolution */
282 unsigned int la_mask; /* what events are recorded by TP LA */
283 unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */
284
285 u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */
286 u32 filter_mask;
287 u32 ingress_config; /* cached TP_INGRESS_CONFIG */
288 /* cached TP_OUT_CONFIG compressed error vector
289 * and passing outer header info for encapsulated packets.
290 */
291 int rx_pkt_encap;
292
293 /*
294 * TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a
295 * subset of the set of fields which may be present in the Compressed
296 * Filter Tuple portion of filters and TCP TCB connections. The
297 * fields which are present are controlled by the TP_VLAN_PRI_MAP.
298 * Since a variable number of fields may or may not be present, their
299 * shifted field positions within the Compressed Filter Tuple may
300 * vary, or not even be present if the field isn't selected in
301 * TP_VLAN_PRI_MAP. Since some of these fields are needed in various
302 * places we store their offsets here, or a -1 if the field isn't
303 * present.
304 */
305 int fcoe_shift;
306 int port_shift;
307 int vnic_shift;
308 int vlan_shift;
309 int tos_shift;
310 int protocol_shift;
311 int ethertype_shift;
312 int macmatch_shift;
313 int matchtype_shift;
314 int frag_shift;
315 };
316
317 struct vpd_params {
318 unsigned int cclk;
319 u8 ec[EC_LEN + 1];
320 u8 sn[SERNUM_LEN + 1];
321 u8 id[ID_LEN + 1];
322 u8 pn[PN_LEN + 1];
323 u8 na[MACADDR_LEN + 1];
324 };
325
326 /*
327 * Maximum resources provisioned for a PCI PF.
328 */
329 struct pf_resources {
330 unsigned int nvi; /* N virtual interfaces */
331 unsigned int neq; /* N egress Qs */
332 unsigned int nethctrl; /* N egress ETH or CTRL Qs */
333 unsigned int niqflint; /* N ingress Qs/w free list(s) & intr */
334 unsigned int tc; /* PCI-E traffic class */
335 unsigned int pmask; /* port access rights mask */
336 unsigned int nexactf; /* N exact MPS filters */
337 unsigned int r_caps; /* read capabilities */
338 unsigned int wx_caps; /* write/execute capabilities */
339 };
340
341 struct pci_params {
342 uint16_t vendor_id;
343 uint16_t device_id;
344 uint32_t vpd_cap_addr;
345 uint16_t speed;
346 uint8_t width;
347 };
348
349 /*
350 * Firmware device log.
351 */
352 struct devlog_params {
353 u32 memtype; /* which memory (EDC0, EDC1, MC) */
354 u32 start; /* start of log in firmware memory */
355 u32 size; /* size of log */
356 };
357
358 /* Stores chip specific parameters */
359 struct arch_specific_params {
360 u8 nchan;
361 u8 pm_stats_cnt;
362 u8 cng_ch_bits_log; /* congestion channel map bits width */
363 u16 mps_rplc_size;
364 u16 vfcount;
365 u32 sge_fl_db;
366 u16 mps_tcam_size;
367 };
368
369 struct adapter_params {
370 struct sge_params sge;
371 struct tp_params tp;
372 struct vpd_params vpd;
373 struct pf_resources pfres;
374 struct pci_params pci;
375 struct devlog_params devlog;
376 enum pcie_memwin drv_memwin;
377
378 unsigned int sf_size; /* serial flash size in bytes */
379 unsigned int sf_nsec; /* # of flash sectors */
380
381 unsigned int fw_vers; /* firmware version */
382 unsigned int bs_vers; /* bootstrap version */
383 unsigned int tp_vers; /* TP microcode version */
384 unsigned int er_vers; /* expansion ROM version */
385 unsigned int scfg_vers; /* Serial Configuration version */
386 unsigned int vpd_vers; /* VPD version */
387
388 unsigned short mtus[NMTUS];
389 unsigned short a_wnd[NCCTRL_WIN];
390 unsigned short b_wnd[NCCTRL_WIN];
391
392 unsigned int mc_size; /* MC memory size */
393 unsigned int nfilters; /* size of filter region */
394
395 unsigned int cim_la_size;
396
397 unsigned char nports; /* # of ethernet ports */
398 unsigned char portvec;
399 unsigned char offload;
400
401 unsigned char bypass;
402 unsigned char hash_filter;
403
404 enum chip_type chip; /* chip code */
405 struct arch_specific_params arch; /* chip specific params */
406
407 unsigned int ofldq_wr_cred;
408
409 unsigned int nsched_cls; /* number of traffic classes */
410
411 unsigned int max_ordird_qp; /* Max read depth per RDMA QP */
412 unsigned int max_ird_adapter; /* Max read depth per adapter */
413 bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */
414 unsigned char ulp_t10dif; /* t10dif support for ulp */
415 unsigned char ulp_crypto; /* Crypto support */
416 bool fr_nsmr_tpte_wr_support; /* FW support for FR_NSMR_TPTE_WR */
417 bool filter2_wr_support; /* FW support for FILTER2_WR */
418 bool viid_smt_extn_support; /* FW returns vin and smt index? */
419 u8 fw_caps_support; /* 32-bit Port Capabilities */
420
421 /*
422 * MPS Buffer Group Map[per Port]. Bit i is set if buffer group i is
423 * used by the Port
424 */
425 u8 mps_bg_map[MAX_NPORTS]; /* MPS Buffer Group Map */
426 bool write_w_imm_support; /* FW supports WRITE_WITH_IMMEDIATE */
427 bool write_cmpl_support; /* FW supports WRITE_CMPL */
428 /* FW supports adding source mac address to TCAM */
429 bool smac_add_support;
430 };
431
432 /*
433 * State needed to monitor the forward progress of SGE Ingress DMA activities
434 * and possible hangs.
435 */
436 struct sge_idma_monitor_state {
437 unsigned int idma_1s_thresh; /* 1s threshold in Core Clock ticks */
438 unsigned int idma_stalled[2]; /* synthesized stalled timers in HZ */
439 unsigned int idma_state[2]; /* IDMA Hang detect state */
440 unsigned int idma_qid[2]; /* IDMA Hung Ingress Queue ID */
441 unsigned int idma_warn[2]; /* time to warning in HZ */
442 };
443
444 /*
445 * Firmware Mailbox Command/Reply log. All values are in Host-Endian format.
446 * The access and execute times are signed in order to accommodate negative
447 * error returns.
448 */
449 struct mbox_cmd {
450 u64 cmd[MBOX_LEN/8]; /* a Firmware Mailbox Command/Reply */
451 u64 timestamp; /* OS-dependent timestamp */
452 u32 seqno; /* sequence number */
453 s16 access; /* time (ms) to access mailbox */
454 s16 execute; /* time (ms) to execute */
455 };
456
457 struct mbox_cmd_log {
458 unsigned int size; /* number of entries in the log */
459 unsigned int cursor; /* next position in the log to write */
460 u32 seqno; /* next sequence number */
461 /* variable length mailbox command log starts here */
462 };
463
464 struct mbox_cmd *mbox_cmd_log_entry(struct mbox_cmd_log *log,
465 unsigned int entry_idx);
466
467 #include <t4fw_interface.h>
468
469 #define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf)
470
471 struct fw_info {
472 u8 chip;
473 char *fs_name;
474 char *fw_mod_name;
475 struct fw_hdr fw_hdr; /* XXX: waste of space, need a sparse struct */
476 };
477
478 struct trace_params {
479 u32 data[TRACE_LEN / 4];
480 u32 mask[TRACE_LEN / 4];
481 unsigned short snap_len;
482 unsigned short min_len;
483 unsigned char skip_ofst;
484 unsigned char skip_len;
485 unsigned char invert;
486 unsigned char port;
487 };
488
489 /*
490 * Firmware Port Capabilities types.
491 */
492 typedef u16 fw_port_cap16_t; /* 16-bit Port Capabilities integral value */
493 typedef u32 fw_port_cap32_t; /* 32-bit Port Capabilities integral value */
494
495 enum fw_caps {
496 FW_CAPS_UNKNOWN = 0, /* 0'ed out initial state */
497 FW_CAPS16 = 1, /* old Firmware: 16-bit Port Capabilities */
498 FW_CAPS32 = 2, /* new Firmware: 32-bit Port Capabilities */
499 };
500
501 struct link_config {
502 fw_port_cap32_t pcaps; /* link capabilities */
503 fw_port_cap32_t acaps; /* advertised capabilities */
504 fw_port_cap32_t lpacaps; /* peer advertised capabilities */
505
506 fw_port_cap32_t link_caps; /* current link capabilities */
507 fw_port_cap32_t admin_caps; /* admin configured link capabilities */
508
509 unsigned char link_ok; /* link up? */
510 unsigned char link_down_rc; /* link down reason */
511
512 /*
513 * State variables between Common Code and OS-dependent "contract"
514 * routines. These are used to communicate information and desired
515 * actions out-of-band.
516 */
517 bool new_module; /* ->OS Transceiver Module inserted */
518 bool redo_l1cfg; /* ->CC redo current "sticky" L1 CFG */
519 };
520
521 /*
522 * Partial EEPROM Vital Product Data structure. Includes only the ID and
523 * VPD-R sections.
524 */
525 struct t4_vpd_hdr {
526 u8 id_tag;
527 u8 id_len[2];
528 u8 id_data[ID_LEN];
529 u8 vpdr_tag;
530 u8 vpdr_len[2];
531 };
532
533 #if _KERNEL
534 #include "adapter.h"
535
536 #ifndef PCI_VENDOR_ID_CHELSIO
537 # define PCI_VENDOR_ID_CHELSIO 0x1425
538 #endif
539
540 #define for_each_port(adapter, iter) \
541 for (iter = 0; iter < (adapter)->params.nports; ++iter)
542
543 int is_offload(const struct adapter *adap);
544 unsigned int core_ticks_per_usec(const struct adapter *adap);
545 unsigned int us_to_core_ticks(const struct adapter *adap,
546 unsigned int us);
547 unsigned int dack_ticks_to_usec(const struct adapter *adap,
548 unsigned int ticks);
549 void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, u32 val);
550
551 void t4_record_mbox_marker(struct adapter *adapter,
552 const void *marker, unsigned int size);
553 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
554 int size, void *rpl, bool sleep_ok, int timeout);
555 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
556 void *rpl, bool sleep_ok);
557
558 int t4_wr_mbox_timeout(struct adapter *adap, int mbox,
559 const void *cmd, int size, void *rpl,
560 int timeout);
561 int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd,
562 int size, void *rpl);
563 int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd,
564 int size, void *rpl);
565 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
566 unsigned int data_reg, u32 *vals, unsigned int nregs,
567 unsigned int start_idx);
568 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
569 unsigned int data_reg, const u32 *vals,
570 unsigned int nregs, unsigned int start_idx);
571
572 void t4_hw_pci_read_cfg4(adapter_t *adapter, int reg, u32 *val);
573
574 struct fw_filter_wr;
575
576 void t4_intr_enable(struct adapter *adapter);
577 void t4_intr_disable(struct adapter *adapter);
578 int t4_slow_intr_handler(struct adapter *adapter);
579
580 int t4_hash_mac_addr(const u8 *addr);
581
582 unsigned int t4_link_fwcap_to_speed(fw_port_cap32_t caps);
583 fw_port_cap32_t t4_link_fwcap_to_fwspeed(fw_port_cap32_t acaps);
584 int t4_link_set_autoneg(struct port_info *pi, u8 autoneg,
585 fw_port_cap32_t *new_caps);
586 int t4_link_set_pause(struct port_info *pi, cc_pause_t pause,
587 fw_port_cap32_t *new_caps);
588 int t4_link_set_fec(struct port_info *pi, cc_fec_t fec,
589 fw_port_cap32_t *new_caps);
590 int t4_link_set_speed(struct port_info *pi, fw_port_cap32_t speed, u8 en,
591 fw_port_cap32_t *new_caps);
592 int t4_link_l1cfg_core(struct adapter *adapter, unsigned int mbox,
593 unsigned int port, struct link_config *lc,
594 fw_port_cap32_t rcap, bool sleep_ok, int timeout);
t4_link_l1cfg(struct adapter * adapter,unsigned int mbox,unsigned int port,struct link_config * lc,fw_port_cap32_t rcap)595 static inline int t4_link_l1cfg(struct adapter *adapter, unsigned int mbox,
596 unsigned int port, struct link_config *lc,
597 fw_port_cap32_t rcap)
598 {
599 return t4_link_l1cfg_core(adapter, mbox, port, lc, rcap,
600 true, FW_CMD_MAX_TIMEOUT);
601 }
t4_link_l1cfg_ns(struct adapter * adapter,unsigned int mbox,unsigned int port,struct link_config * lc,fw_port_cap32_t rcap)602 static inline int t4_link_l1cfg_ns(struct adapter *adapter, unsigned int mbox,
603 unsigned int port, struct link_config *lc,
604 fw_port_cap32_t rcap)
605 {
606 return t4_link_l1cfg_core(adapter, mbox, port, lc, rcap,
607 false, FW_CMD_MAX_TIMEOUT);
608 }
609
610 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port);
611 int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data);
612 int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data);
613 int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz);
614 int t4_seeprom_wp(struct adapter *adapter, int enable);
615 int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p);
616 int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p);
617 int t4_get_pfres(struct adapter *adapter);
618 int t4_read_flash(struct adapter *adapter, unsigned int addr, unsigned int nwords,
619 u32 *data, int byte_oriented);
620 int t4_write_flash(struct adapter *adapter, unsigned int addr,
621 unsigned int n, const u8 *data, int byte_oriented);
622 int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size,
623 unsigned int bootstrap);
624 int t4_load_phy_fw(struct adapter *adap,
625 int win, t4_os_lock_t *lock,
626 int (*phy_fw_version)(const u8 *, size_t),
627 const u8 *phy_fw_data, size_t phy_fw_size);
628 int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver);
629 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op);
630 int t5_fw_init_extern_mem(struct adapter *adap);
631 #ifdef CHELSIO_T4_DIAGS
632 int t4_erase_sf(struct adapter *adapter);
633 #endif
634 int t4_load_bootcfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size);
635 int t4_read_bootcfg(struct adapter *adap, u8 *cfg_data, unsigned int size);
636 int t4_load_boot(struct adapter *adap, u8 *boot_data,
637 unsigned int boot_addr, unsigned int size);
638 int t4_flash_erase_sectors(struct adapter *adapter, int start, int end);
639 int t4_flash_cfg_addr(struct adapter *adapter);
640 int t4_check_fw_version(struct adapter *adap);
641 int t4_load_cfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size);
642 int t4_get_fw_version(struct adapter *adapter, u32 *vers);
643 int t4_get_bs_version(struct adapter *adapter, u32 *vers);
644 int t4_get_tp_version(struct adapter *adapter, u32 *vers);
645 int t4_get_exprom_version(struct adapter *adapter, u32 *vers);
646 int t4_get_scfg_version(struct adapter *adapter, u32 *vers);
647 int t4_get_vpd_version(struct adapter *adapter, u32 *vers);
648 int t4_get_version_info(struct adapter *adapter);
649 void t4_dump_version_info(struct adapter *adapter);
650 int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info,
651 const u8 *fw_data, unsigned int fw_size,
652 struct fw_hdr *card_fw, const int t4_fw_install,
653 enum dev_state state, int *reset);
654 int t4_wait_dev_ready(struct adapter *adapter);
655 enum chip_type t4_get_chip_type(struct adapter *adap, int ver);
656 int t4_prep_adapter(struct adapter *adapter, bool reset);
657 int t4_prep_pf(struct adapter *adapter);
658 int t4_prep_master_pf(struct adapter *adapter);
659 int t4_shutdown_adapter(struct adapter *adapter);
660
661 enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS };
662 int t4_bar2_sge_qregs(struct adapter *adapter,
663 unsigned int qid,
664 enum t4_bar2_qtype qtype,
665 int user,
666 u64 *pbar2_qoffset,
667 unsigned int *pbar2_qid);
668
669 int t4_init_devlog_params(struct adapter *adapter, int fw_attach);
670 int t4_init_sge_params(struct adapter *adapter);
671 int t4_init_tp_params(struct adapter *adap, bool sleep_ok);
672 int t4_filter_field_shift(const struct adapter *adap, int filter_sel);
673 int t4_create_filter_info(const struct adapter *adapter,
674 u64 *filter_value, u64 *filter_mask,
675 int fcoe, int port, int vnic_id,
676 int vlan, int vlan_pcp, int vlan_dei,
677 int tos, int protocol, int ethertype,
678 int macmatch, int mpshittype, int fragmentation);
679 int t4_init_rss_mode(struct adapter *adap, int mbox);
680 int t4_init_portinfo_viid(struct port_info *pi, int mbox,
681 int port, int pf, int vf, u8 mac[], bool alloc_vi);
682 int t4_init_portinfo(struct port_info *pi, int mbox,
683 int port, int pf, int vf, u8 mac[]);
684 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf);
685 int t4_mirror_init(struct adapter *adap, int mbox, int pf, int vf,
686 bool enable_mirror);
687 void t4_fatal_err(struct adapter *adapter);
688 void t4_db_full(struct adapter *adapter);
689 void t4_db_dropped(struct adapter *adapter);
690 int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp,
691 int filter_index, int enable);
692 void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp,
693 int filter_index, int *enabled);
694 unsigned int t4_chip_rss_size(struct adapter *adapter);
695 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
696 int start, int n, const u16 *rspq, unsigned int nrspq);
697 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
698 unsigned int flags);
699 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
700 unsigned int flags, unsigned int defq, unsigned int skeyidx,
701 unsigned int skey);
702 int t4_read_rss(struct adapter *adapter, u16 *entries);
703 void t4_read_rss_key(struct adapter *adapter, u32 *key, bool sleep_ok);
704 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx,
705 bool sleep_ok);
706 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index,
707 u32 *valp, bool sleep_ok);
708 void t4_write_rss_pf_config(struct adapter *adapter, unsigned int index,
709 u32 val, bool sleep_ok);
710 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index,
711 u32 *vfl, u32 *vfh, bool sleep_ok);
712 u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok);
713 u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok);
714 unsigned int t4_get_mps_bg_map(struct adapter *adapter, int pidx);
715 unsigned int t4_get_tp_e2c_map(struct adapter *adapter, int pidx);
716 unsigned int t4_get_tp_ch_map(struct adapter *adapter, int pidx);
717 int t4_mps_set_active_ports(struct adapter *adap, unsigned int port_mask);
718 int t4_read_tcb(struct adapter *adap, int win, int tid, u32 tcb[TCB_SIZE/4]);
719 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]);
720 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]);
721 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres);
722 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n);
723 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n);
724 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
725 unsigned int *valp);
726 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
727 const unsigned int *valp);
728 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr);
729 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp,
730 unsigned int *pif_req_wrptr, unsigned int *pif_rsp_wrptr);
731 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp);
732 int t4_get_flash_params(struct adapter *adapter);
733
734 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg, int drv_fw_attach);
735 int t4_get_util_window(struct adapter *adap, int drv_fw_attach);
736 void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window);
737 void t4_idma_monitor_init(struct adapter *adapter,
738 struct sge_idma_monitor_state *idma);
739 void t4_idma_monitor(struct adapter *adapter,
740 struct sge_idma_monitor_state *idma,
741 int hz, int ticks);
742 int t4_set_vf_mac_acl(struct adapter *adapter, unsigned int vf,
743 unsigned int naddr, u8 *addr);
744
745 #define T4_MEMORY_WRITE 0
746 #define T4_MEMORY_READ 1
747 int t4_memory_rw_addr(struct adapter *adap, int win,
748 u32 addr, u32 len,
749 void *hbuf, int dir);
750 int t4_memory_rw_mtype(struct adapter *adap, int win,
751 int mtype, u32 maddr, u32 len,
752 void *hbuf, int dir);
753
754 int t4_memory_rw(struct adapter *adap, int win,
755 int mtype, u32 maddr, u32 len,
756 void *hbuf, int dir);
757 int hash_mac_addr(const u8 *addr);
758
759 bool t4_is_inserted_mod_type(unsigned int fw_mod_type);
760 extern unsigned int t4_get_regs_len(struct adapter *adapter);
761 extern void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size);
762
763 const char *t4_get_port_type_description(enum fw_port_type port_type);
764 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p);
765 void t4_get_port_stats_offset(struct adapter *adap, int idx,
766 struct port_stats *stats,
767 struct port_stats *offset);
768 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p);
769 void t4_clr_port_stats(struct adapter *adap, int idx);
770
771 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log);
772 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]);
773 void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED]);
774 void t4_get_tx_sched(struct adapter *adap, unsigned int sched, unsigned int *kbps,
775 unsigned int *ipg, bool sleep_ok);
776 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
777 unsigned int mask, unsigned int val);
778 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr);
779 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st,
780 bool sleep_ok);
781 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st,
782 bool sleep_ok);
783 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st,
784 bool sleep_ok);
785 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st,
786 bool sleep_ok);
787 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
788 struct tp_tcp_stats *v6, bool sleep_ok);
789 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx,
790 struct tp_fcoe_stats *st, bool sleep_ok);
791 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
792 const unsigned short *alpha, const unsigned short *beta);
793
794 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf);
795
796 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate);
797 int t4_set_filter_mode(struct adapter *adap, unsigned int mode_map,
798 bool sleep_ok);
799 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr,
800 int rqtype, int qid);
801
802 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
803 enum dev_master master, enum dev_state *state);
804 int t4_fw_bye(struct adapter *adap, unsigned int mbox);
805 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset);
806 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
807 const u8 *fw_data, unsigned int size, int force);
808 int t4_fl_pkt_align(struct adapter *adap, bool is_packed);
809 int t4_fixup_host_params_compat(struct adapter *adap, unsigned int page_size,
810 unsigned int cache_line_size,
811 enum chip_type chip_compat);
812 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
813 unsigned int cache_line_size);
814 int t4_fw_initialize(struct adapter *adap, unsigned int mbox);
815 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
816 unsigned int vf, unsigned int nparams, const u32 *params,
817 u32 *val);
818 int t4_query_params_ns(struct adapter *adap, unsigned int mbox, unsigned int pf,
819 unsigned int vf, unsigned int nparams, const u32 *params,
820 u32 *val);
821 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf,
822 unsigned int vf, unsigned int nparams, const u32 *params,
823 u32 *val, int rw, bool sleep_ok);
824 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
825 unsigned int pf, unsigned int vf,
826 unsigned int nparams, const u32 *params,
827 const u32 *val, int timeout);
828 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
829 unsigned int vf, unsigned int nparams, const u32 *params,
830 const u32 *val);
831 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
832 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
833 unsigned int rxqi, unsigned int rxq, unsigned int tc,
834 unsigned int vi, unsigned int cmask, unsigned int pmask,
835 unsigned int exactf, unsigned int rcaps, unsigned int wxcaps);
836 int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox,
837 unsigned int port, unsigned int pf, unsigned int vf,
838 unsigned int nmac, u8 *mac, unsigned int *rss_size,
839 u8 *vivld, u8 *vin,
840 unsigned int portfunc, unsigned int idstype);
841 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
842 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
843 unsigned int *rss_size, u8 *vivld, u8 *vin);
844 int t4_free_vi(struct adapter *adap, unsigned int mbox,
845 unsigned int pf, unsigned int vf,
846 unsigned int viid);
847 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
848 int mtu, int promisc, int all_multi, int bcast, int vlanex,
849 bool sleep_ok);
850 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, unsigned int viid,
851 bool free, unsigned int naddr, const u8 **addr, u16 *idx,
852 u64 *hash, bool sleep_ok);
853 int t4_free_mac_filt(struct adapter *adap, unsigned int mbox,
854 unsigned int viid, unsigned int naddr,
855 const u8 **addr, bool sleep_ok);
856 int t4_free_encap_mac_filt(struct adapter *adap, unsigned int viid,
857 int idx, bool sleep_ok);
858 int t4_free_raw_mac_filt(struct adapter *adap, unsigned int viid,
859 const u8 *addr, const u8 *mask, unsigned int idx,
860 u8 lookup_type, u8 port_id, bool sleep_ok);
861 int t4_alloc_raw_mac_filt(struct adapter *adap, unsigned int viid,
862 const u8 *addr, const u8 *mask, unsigned int idx,
863 u8 lookup_type, u8 port_id, bool sleep_ok);
864 int t4_alloc_encap_mac_filt(struct adapter *adap, unsigned int viid,
865 const u8 *addr, const u8 *mask, unsigned int vni,
866 unsigned int vni_mask, u8 dip_hit, u8 lookup_type,
867 bool sleep_ok);
868 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
869 int idx, const u8 *addr, bool persist, u8 *smt_idx);
870 int t4_del_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
871 const u8 *addr, bool smac);
872 int t4_add_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
873 int idx, const u8 *addr, bool persist, u8 *smt_idx, bool smac);
874 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
875 bool ucast, u64 vec, bool sleep_ok);
876 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
877 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en);
878 int t4_enable_pi_params(struct adapter *adap, unsigned int mbox,
879 struct port_info *pi,
880 bool rx_en, bool tx_en, bool dcb_en);
881 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
882 bool rx_en, bool tx_en);
883 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
884 unsigned int nblinks);
885 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
886 unsigned int mmd, unsigned int reg, unsigned int *valp);
887 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
888 unsigned int mmd, unsigned int reg, unsigned int val);
889 int t4_i2c_io(struct adapter *adap, unsigned int mbox,
890 int port, unsigned int devid,
891 unsigned int offset, unsigned int len,
892 u8 *buf, bool write);
893 int t4_i2c_rd(struct adapter *adap, unsigned int mbox,
894 int port, unsigned int devid,
895 unsigned int offset, unsigned int len,
896 u8 *buf);
897 int t4_i2c_wr(struct adapter *adap, unsigned int mbox,
898 int port, unsigned int devid,
899 unsigned int offset, unsigned int len,
900 u8 *buf);
901 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf,
902 unsigned int vf, unsigned int iqtype, unsigned int iqid,
903 unsigned int fl0id, unsigned int fl1id);
904 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
905 unsigned int vf, unsigned int iqtype, unsigned int iqid,
906 unsigned int fl0id, unsigned int fl1id);
907 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
908 unsigned int vf, unsigned int eqid);
909 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
910 unsigned int vf, unsigned int eqid);
911 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
912 unsigned int vf, unsigned int eqid);
913 int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid,
914 enum ctxt_type ctype, u32 *data);
915 int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid, enum ctxt_type ctype,
916 u32 *data);
917 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox, int ctxt_type);
918 int t4_read_sge_dbqtimers(struct adapter *adap, unsigned int ndbqtimers,
919 u16 *dbqtimers);
920 const char *t4_link_down_rc_str(unsigned char link_down_rc);
921 void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl);
922 int t4_update_port_info(struct port_info *pi);
923 int t4_get_link_params(struct port_info *pi, unsigned int *link_okp,
924 unsigned int *speedp, unsigned int *mtup);
925 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl);
926 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, u32 addr, u32 val);
927
928 int t4_sched_config(struct adapter *adapter, int type, int minmaxen);
929 int t4_sched_params(struct adapter *adapter,
930 int channel, int cls,
931 int level, int mode, int type,
932 int rateunit, int ratemode,
933 int minrate, int maxrate, int weight,
934 int pktsize, int burstsize);
935 int t4_read_sched_params(struct adapter *adapter,
936 int channel, int cls,
937 int *level, int *mode, int *type,
938 int *rateunit, int *ratemode,
939 int *minrate, int *maxrate, int *weight,
940 int *pktsize, int *burstsize);
941 int t4_config_watchdog(struct adapter *adapter, unsigned int mbox,
942 unsigned int pf, unsigned int vf,
943 unsigned int timeout, unsigned int action);
944 int t4_get_devlog_level(struct adapter *adapter, unsigned int *level);
945 int t4_set_devlog_level(struct adapter *adapter, unsigned int level);
946
947 void t4_sge_decode_idma_state(struct adapter *adapter, int state);
948
949 void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs,
950 u32 start_index, bool sleep_ok);
951 void t4_tp_pio_write(struct adapter *adap, u32 *buff, u32 nregs,
952 u32 start_index, bool sleep_ok);
953 void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs,
954 u32 start_index, bool sleep_ok);
955 void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs,
956 u32 start_index, bool sleep_ok);
957 int t4_configure_ringbb(struct adapter *adap);
958 int t4_configure_add_smac(struct adapter *adap);
959 int t4_set_vlan_acl(struct adapter *adap, unsigned int mbox, unsigned int vf,
960 u16 vlan);
961 #endif
962 #ifdef __cplusplus
963 }
964 #endif
965 #endif /* __CHELSIO_COMMON_H */
966