Searched refs:speed_cap_mask (Results 1 – 8 of 8) sorted by relevance
211 if (!(pLM->params.link.speed_cap_mask[i] & in BnxeHwReqPhyMediumSettings()222 if (!(pLM->params.link.speed_cap_mask[i] & in BnxeHwReqPhyMediumSettings()233 if (!(pLM->params.link.speed_cap_mask[i] & in BnxeHwReqPhyMediumSettings()244 if (!(pLM->params.link.speed_cap_mask[i] & in BnxeHwReqPhyMediumSettings()255 if (!(pLM->params.link.speed_cap_mask[i] & in BnxeHwReqPhyMediumSettings()266 if (!(pLM->params.link.speed_cap_mask[i] & in BnxeHwReqPhyMediumSettings()277 if (!(pLM->params.link.speed_cap_mask[i] & in BnxeHwReqPhyMediumSettings()288 if (!(pLM->params.link.speed_cap_mask[i] & in BnxeHwReqPhyMediumSettings()
455 speed_cap_mask[cfg_idx])); in elink_check_lfa()457 if (cur_speed_cap_mask != params->speed_cap_mask[cfg_idx]) { in elink_check_lfa()460 params->speed_cap_mask[cfg_idx]); in elink_check_lfa()3747 params->phy[actual_phy_idx].speed_cap_mask = in set_phy_vars()3748 params->speed_cap_mask[link_cfg_idx]; in set_phy_vars()3761 params->phy[actual_phy_idx].speed_cap_mask); in set_phy_vars()4061 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || in elink_warpcore_enable_AN_KR()4071 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) || in elink_warpcore_enable_AN_KR()4134 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) || in elink_warpcore_enable_AN_KR()4779 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G) in elink_sfp_e3_set_transmitter()[all …]
339 u32 speed_cap_mask; member399 u32 speed_cap_mask[ELINK_LINK_CONFIG_SIZE]; member
1465 if (pdev->params.link.speed_cap_mask[0] & PORT_HW_CFG_SPEED_CAPABILITY2_D0_20G) in lm_init_phy()1483 if (pdev->params.link.speed_cap_mask[0] & PORT_HW_CFG_SPEED_CAPABILITY2_D0_20G) in lm_init_phy()1487 else if (pdev->params.link.speed_cap_mask[0] & PORT_HW_CFG_SPEED_CAPABILITY2_D0_10G) in lm_init_phy()
2045 pdev->params.link.speed_cap_mask[0] = val & PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK; in lm_get_shmem_port_hw_config()2049 pdev->params.link.speed_cap_mask[1] = val & PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK; in lm_get_shmem_port_hw_config()2081 …( FALSE == ( pdev->params.link.speed_cap_mask[0] & (PORT_HW_CFG_SPEED_CAPABILITY_D0_10G | PORT_HW_… in lm_get_shmem_port_hw_config()
907 u32 speed_cap_mask[SHMEM_LINK_CONFIG_SIZE]; member
1169 u32 speed_cap_mask; /* 0x14 */ member
3388 offsetof(struct nvm_cfg1_port, speed_cap_mask)); in ecore_hw_get_nvm_info()