xref: /illumos-gate/usr/src/uts/common/io/bnxe/577xx/hsi/mcp/shmem.h (revision cabd62a218e426e3dea29d3051d184458cdddbdf)
1 #ifndef __shmem_h__
2 #define __shmem_h__
3 
4 #if !defined(__LITTLE_ENDIAN) && !defined(__BIG_ENDIAN)
5 	#error "Missing either LITTLE_ENDIAN or BIG_ENDIAN definition."
6 #endif
7 
8 #define FUNC_0              0
9 #define FUNC_1              1
10 #define FUNC_2              2
11 #define FUNC_3              3
12 #define FUNC_4              4
13 #define FUNC_5              5
14 #define FUNC_6              6
15 #define FUNC_7              7
16 #define E1_FUNC_MAX         2
17 #define E1H_FUNC_MAX            8
18 #define E2_FUNC_MAX         4   /* per path */
19 
20 #define VN_0                0
21 #define VN_1                1
22 #define VN_2                2
23 #define VN_3                3
24 #define E1VN_MAX            1
25 #define E1HVN_MAX           4
26 
27 #define E2_VF_MAX           64  /* HC_REG_VF_CONFIGURATION_SIZE */
28 /* This value (in milliseconds) determines the frequency of the driver
29  * issuing the PULSE message code.  The firmware monitors this periodic
30  * pulse to determine when to switch to an OS-absent mode. */
31 #define DRV_PULSE_PERIOD_MS     250
32 
33 /* This value (in milliseconds) determines how long the driver should
34  * wait for an acknowledgement from the firmware before timing out.  Once
35  * the firmware has timed out, the driver will assume there is no firmware
36  * running and there won't be any firmware-driver synchronization during a
37  * driver reset. */
38 #define FW_ACK_TIME_OUT_MS      5000
39 
40 #define FW_ACK_POLL_TIME_MS     1
41 
42 #define FW_ACK_NUM_OF_POLL  (FW_ACK_TIME_OUT_MS/FW_ACK_POLL_TIME_MS)
43 
44 #define MFW_TRACE_SIGNATURE     0x54524342
45 
46 /****************************************************************************
47  * Driver <-> FW Mailbox                                                    *
48  ****************************************************************************/
49 struct drv_port_mb {
50 
51 	u32 link_status;
52 	/* Driver should update this field on any link change event */
53 
54 	#define LINK_STATUS_NONE				(0<<0)
55 	#define LINK_STATUS_LINK_FLAG_MASK			0x00000001
56 	#define LINK_STATUS_LINK_UP				0x00000001
57 	#define LINK_STATUS_SPEED_AND_DUPLEX_MASK		0x0000001E
58 	#define LINK_STATUS_SPEED_AND_DUPLEX_AN_NOT_COMPLETE	(0<<1)
59 	#define LINK_STATUS_SPEED_AND_DUPLEX_10THD		(1<<1)
60 	#define LINK_STATUS_SPEED_AND_DUPLEX_10TFD		(2<<1)
61 	#define LINK_STATUS_SPEED_AND_DUPLEX_100TXHD		(3<<1)
62 	#define LINK_STATUS_SPEED_AND_DUPLEX_100T4		(4<<1)
63 	#define LINK_STATUS_SPEED_AND_DUPLEX_100TXFD		(5<<1)
64 	#define LINK_STATUS_SPEED_AND_DUPLEX_1000THD		(6<<1)
65 	#define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD		(7<<1)
66 	#define LINK_STATUS_SPEED_AND_DUPLEX_1000XFD		(7<<1)
67 	#define LINK_STATUS_SPEED_AND_DUPLEX_2500THD		(8<<1)
68 	#define LINK_STATUS_SPEED_AND_DUPLEX_2500TFD		(9<<1)
69 	#define LINK_STATUS_SPEED_AND_DUPLEX_2500XFD		(9<<1)
70 	#define LINK_STATUS_SPEED_AND_DUPLEX_10GTFD		(10<<1)
71 	#define LINK_STATUS_SPEED_AND_DUPLEX_10GXFD		(10<<1)
72 	#define LINK_STATUS_SPEED_AND_DUPLEX_20GTFD		(11<<1)
73 	#define LINK_STATUS_SPEED_AND_DUPLEX_20GXFD		(11<<1)
74 
75 	#define LINK_STATUS_AUTO_NEGOTIATE_FLAG_MASK		0x00000020
76 	#define LINK_STATUS_AUTO_NEGOTIATE_ENABLED		0x00000020
77 
78 	#define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE		0x00000040
79 	#define LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK	0x00000080
80 	#define LINK_STATUS_PARALLEL_DETECTION_USED		0x00000080
81 
82 	#define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE	0x00000200
83 	#define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE	0x00000400
84 	#define LINK_STATUS_LINK_PARTNER_100T4_CAPABLE		0x00000800
85 	#define LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE	0x00001000
86 	#define LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE	0x00002000
87 	#define LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE		0x00004000
88 	#define LINK_STATUS_LINK_PARTNER_10THD_CAPABLE		0x00008000
89 
90 	#define LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK		0x00010000
91 	#define LINK_STATUS_TX_FLOW_CONTROL_ENABLED		0x00010000
92 
93 	#define LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK		0x00020000
94 	#define LINK_STATUS_RX_FLOW_CONTROL_ENABLED		0x00020000
95 
96 	#define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK	0x000C0000
97 	#define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE	(0<<18)
98 	#define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE	(1<<18)
99 	#define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE	(2<<18)
100 	#define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE		(3<<18)
101 
102 	#define LINK_STATUS_SERDES_LINK				0x00100000
103 
104 	#define LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE	0x00200000
105 	#define LINK_STATUS_LINK_PARTNER_2500XHD_CAPABLE	0x00400000
106 	#define LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE		0x00800000
107 	#define LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE		0x10000000
108 
109 	#define LINK_STATUS_PFC_ENABLED				0x20000000
110 
111 	#define LINK_STATUS_PHYSICAL_LINK_FLAG			0x40000000
112 	#define LINK_STATUS_SFP_TX_FAULT			0x80000000
113 
114 	u32 port_stx;
115 
116 	u32 stat_nig_timer;
117 
118 	/* MCP firmware does not use this field */
119 	u32 ext_phy_fw_version;
120 
121 };
122 
123 
124 struct drv_func_mb {
125 
126 	u32 drv_mb_header;
127 	#define DRV_MSG_CODE_MASK                       0xffff0000
128 	#define DRV_MSG_CODE_LOAD_REQ                   0x10000000
129 	#define DRV_MSG_CODE_LOAD_DONE                  0x11000000
130 	#define DRV_MSG_CODE_UNLOAD_REQ_WOL_EN          0x20000000
131 	#define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS         0x20010000
132 	#define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP         0x20020000
133 	#define DRV_MSG_CODE_UNLOAD_DONE                0x21000000
134 	#define DRV_MSG_CODE_DCC_OK                     0x30000000
135 	#define DRV_MSG_CODE_DCC_FAILURE                0x31000000
136 	#define DRV_MSG_CODE_DIAG_ENTER_REQ             0x50000000
137 	#define DRV_MSG_CODE_DIAG_EXIT_REQ              0x60000000
138 	#define DRV_MSG_CODE_VALIDATE_KEY               0x70000000
139 	#define DRV_MSG_CODE_GET_CURR_KEY               0x80000000
140 	#define DRV_MSG_CODE_GET_UPGRADE_KEY            0x81000000
141 	#define DRV_MSG_CODE_GET_MANUF_KEY              0x82000000
142 	#define DRV_MSG_CODE_LOAD_L2B_PRAM              0x90000000
143 	#define DRV_MSG_CODE_OEM_OK			0x00010000
144 	#define DRV_MSG_CODE_OEM_FAILURE		0x00020000
145 	#define DRV_MSG_CODE_OEM_UPDATE_SVID_OK		0x00030000
146 	#define DRV_MSG_CODE_OEM_UPDATE_SVID_FAILURE	0x00040000
147 	/*
148 	 * The optic module verification command requires bootcode
149 	 * v5.0.6 or later, te specific optic module verification command
150 	 * requires bootcode v5.2.12 or later
151 	 */
152 	#define DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL     0xa0000000
153 	#define REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL     0x00050006
154 	#define DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL  0xa1000000
155 	#define REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL  0x00050234
156 	#define DRV_MSG_CODE_VRFY_AFEX_SUPPORTED        0xa2000000
157 	#define REQ_BC_VER_4_VRFY_AFEX_SUPPORTED        0x00070002
158 	#define REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED   0x00070014
159 	#define REQ_BC_VER_4_MT_SUPPORTED               0x00070201
160 	#define REQ_BC_VER_4_PFC_STATS_SUPPORTED        0x00070201
161 	#define REQ_BC_VER_4_FCOE_FEATURES              0x00070209
162 
163 	#define DRV_MSG_CODE_DCBX_ADMIN_PMF_MSG         0xb0000000
164 	#define DRV_MSG_CODE_DCBX_PMF_DRV_OK            0xb2000000
165 	#define REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF     0x00070401
166 
167 	#define DRV_MSG_CODE_VF_DISABLED_DONE           0xc0000000
168 
169 	#define DRV_MSG_CODE_AFEX_DRIVER_SETMAC         0xd0000000
170 	#define DRV_MSG_CODE_AFEX_LISTGET_ACK           0xd1000000
171 	#define DRV_MSG_CODE_AFEX_LISTSET_ACK           0xd2000000
172 	#define DRV_MSG_CODE_AFEX_STATSGET_ACK          0xd3000000
173 	#define DRV_MSG_CODE_AFEX_VIFSET_ACK            0xd4000000
174 
175 	#define DRV_MSG_CODE_DRV_INFO_ACK               0xd8000000
176 	#define DRV_MSG_CODE_DRV_INFO_NACK              0xd9000000
177 
178 	#define DRV_MSG_CODE_EEE_RESULTS_ACK            0xda000000
179 
180 	#define DRV_MSG_CODE_RMMOD                      0xdb000000
181 	#define REQ_BC_VER_4_RMMOD_CMD                  0x0007080f
182 
183 	#define DRV_MSG_CODE_SET_MF_BW                  0xe0000000
184 	#define REQ_BC_VER_4_SET_MF_BW                  0x00060202
185 	#define DRV_MSG_CODE_SET_MF_BW_ACK              0xe1000000
186 
187 	#define DRV_MSG_CODE_LINK_STATUS_CHANGED        0x01000000
188 
189 	#define DRV_MSG_CODE_INITIATE_FLR               0x02000000
190 	#define REQ_BC_VER_4_INITIATE_FLR               0x00070213
191 
192 	#define BIOS_MSG_CODE_LIC_CHALLENGE             0xff010000
193 	#define BIOS_MSG_CODE_LIC_RESPONSE              0xff020000
194 	#define BIOS_MSG_CODE_VIRT_MAC_PRIM             0xff030000
195 	#define BIOS_MSG_CODE_VIRT_MAC_ISCSI            0xff040000
196 
197 	#define DRV_MSG_CODE_IMG_OFFSET_REQ             0xe2000000
198 	#define DRV_MSG_CODE_IMG_SIZE_REQ               0xe3000000
199 
200 	#define DRV_MSG_CODE_UFP_CONFIG_ACK             0xe4000000
201 
202 	#define DRV_MSG_SEQ_NUMBER_MASK                 0x0000ffff
203 
204 	u32 drv_mb_param;
205 	#define DRV_MSG_CODE_SET_MF_BW_MIN_MASK         0x00ff0000
206 	#define DRV_MSG_CODE_SET_MF_BW_MAX_MASK         0xff000000
207 
208 	#define DRV_MSG_CODE_UNLOAD_NON_D3_POWER        0x00000001
209 	#define DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET     0x00000002
210 
211 	#define DRV_MSG_CODE_LOAD_REQ_WITH_LFA          0x0000100a
212 	#define DRV_MSG_CODE_LOAD_REQ_FORCE_LFA         0x00002000
213 
214 	#define DRV_MSG_CODE_USR_BLK_IMAGE_REQ          0x00000001
215 	#define DRV_MSG_CODE_ISCSI_PERS_IMAGE_REQ       0x00000002
216 	#define DRV_MSG_CODE_VPD_IMAGE_REQ              0x00000003
217 
218 	u32 fw_mb_header;
219 	#define FW_MSG_CODE_MASK                        0xffff0000
220 	#define FW_MSG_CODE_DRV_LOAD_COMMON             0x10100000
221 	#define FW_MSG_CODE_DRV_LOAD_PORT               0x10110000
222 	#define FW_MSG_CODE_DRV_LOAD_FUNCTION           0x10120000
223 	/* Load common chip is supported from bc 6.0.0  */
224 	#define REQ_BC_VER_4_DRV_LOAD_COMMON_CHIP       0x00060000
225 	#define FW_MSG_CODE_DRV_LOAD_COMMON_CHIP        0x10130000
226 
227 	#define FW_MSG_CODE_DRV_LOAD_REFUSED            0x10200000
228 	#define FW_MSG_CODE_DRV_LOAD_DONE               0x11100000
229 	#define FW_MSG_CODE_DRV_UNLOAD_COMMON           0x20100000
230 	#define FW_MSG_CODE_DRV_UNLOAD_PORT             0x20110000
231 	#define FW_MSG_CODE_DRV_UNLOAD_FUNCTION         0x20120000
232 	#define FW_MSG_CODE_DRV_UNLOAD_DONE             0x21100000
233 	#define FW_MSG_CODE_DCC_DONE                    0x30100000
234 	#define FW_MSG_CODE_LLDP_DONE                   0x40100000
235 	#define FW_MSG_CODE_DIAG_ENTER_DONE             0x50100000
236 	#define FW_MSG_CODE_DIAG_REFUSE                 0x50200000
237 	#define FW_MSG_CODE_DIAG_EXIT_DONE              0x60100000
238 	#define FW_MSG_CODE_VALIDATE_KEY_SUCCESS        0x70100000
239 	#define FW_MSG_CODE_VALIDATE_KEY_FAILURE        0x70200000
240 	#define FW_MSG_CODE_GET_KEY_DONE                0x80100000
241 	#define FW_MSG_CODE_NO_KEY                      0x80f00000
242 	#define FW_MSG_CODE_LIC_INFO_NOT_READY          0x80f80000
243 	#define FW_MSG_CODE_L2B_PRAM_LOADED             0x90100000
244 	#define FW_MSG_CODE_L2B_PRAM_T_LOAD_FAILURE     0x90210000
245 	#define FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE     0x90220000
246 	#define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE     0x90230000
247 	#define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE     0x90240000
248 	#define FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS        0xa0100000
249 	#define FW_MSG_CODE_VRFY_OPT_MDL_INVLD_IMG      0xa0200000
250 	#define FW_MSG_CODE_VRFY_OPT_MDL_UNAPPROVED     0xa0300000
251 	#define FW_MSG_CODE_VF_DISABLED_DONE            0xb0000000
252 	#define FW_MSG_CODE_HW_SET_INVALID_IMAGE        0xb0100000
253 
254 	#define FW_MSG_CODE_AFEX_DRIVER_SETMAC_DONE     0xd0100000
255 	#define FW_MSG_CODE_AFEX_LISTGET_ACK            0xd1100000
256 	#define FW_MSG_CODE_AFEX_LISTSET_ACK            0xd2100000
257 	#define FW_MSG_CODE_AFEX_STATSGET_ACK           0xd3100000
258 	#define FW_MSG_CODE_AFEX_VIFSET_ACK             0xd4100000
259 
260 	#define FW_MSG_CODE_DRV_INFO_ACK                0xd8100000
261 	#define FW_MSG_CODE_DRV_INFO_NACK               0xd9100000
262 
263 	#define FW_MSG_CODE_EEE_RESULS_ACK              0xda100000
264 
265 	#define FW_MSG_CODE_RMMOD_ACK                   0xdb100000
266 
267 	#define FW_MSG_CODE_SET_MF_BW_SENT              0xe0000000
268 	#define FW_MSG_CODE_SET_MF_BW_DONE              0xe1000000
269 
270 	#define FW_MSG_CODE_LINK_CHANGED_ACK            0x01100000
271 
272 	#define FW_MSG_CODE_FLR_ACK                     0x02000000
273 	#define FW_MSG_CODE_FLR_NACK                    0x02100000
274 
275 	#define FW_MSG_CODE_LIC_CHALLENGE               0xff010000
276 	#define FW_MSG_CODE_LIC_RESPONSE                0xff020000
277 	#define FW_MSG_CODE_VIRT_MAC_PRIM               0xff030000
278 	#define FW_MSG_CODE_VIRT_MAC_ISCSI              0xff040000
279 
280 	#define FW_MSG_CODE_IMG_OFFSET_RESPONSE         0xe2100000
281 	#define FW_MSG_CODE_IMG_SIZE_RESPONSE           0xe3100000
282 
283 	#define FW_MSG_CODE_OEM_ACK			0x00010000
284 	#define DRV_MSG_CODE_OEM_UPDATE_SVID_ACK	0x00020000
285 
286 	#define FW_MSG_SEQ_NUMBER_MASK                  0x0000ffff
287 
288 	u32 fw_mb_param;
289 
290 	#define FW_PARAM_INVALID_IMG                    0xffffffff
291 
292 	u32 drv_pulse_mb;
293 	#define DRV_PULSE_SEQ_MASK                      0x00007fff
294 	#define DRV_PULSE_SYSTEM_TIME_MASK              0xffff0000
295 	/*
296 	 * The system time is in the format of
297 	 * (year-2001)*12*32 + month*32 + day.
298 	 */
299 	#define DRV_PULSE_ALWAYS_ALIVE                  0x00008000
300 	/*
301 	 * Indicate to the firmware not to go into the
302 	 * OS-absent when it is not getting driver pulse.
303 	 * This is used for debugging as well for PXE(MBA).
304 	 */
305 
306 	u32 mcp_pulse_mb;
307 	#define MCP_PULSE_SEQ_MASK                      0x00007fff
308 	#define MCP_PULSE_ALWAYS_ALIVE                  0x00008000
309 	/* Indicates to the driver not to assert due to lack
310 	 * of MCP response */
311 	#define MCP_EVENT_MASK                          0xffff0000
312 	#define MCP_EVENT_OTHER_DRIVER_RESET_REQ        0x00010000
313 
314 	u32 iscsi_boot_signature;
315 	u32 iscsi_boot_block_offset;
316 
317 	u32 drv_status;
318 	#define DRV_STATUS_PMF                          0x00000001
319 	#define DRV_STATUS_VF_DISABLED                  0x00000002
320 	#define DRV_STATUS_SET_MF_BW                    0x00000004
321 	#define DRV_STATUS_LINK_EVENT                   0x00000008
322 
323 	#define DRV_STATUS_OEM_EVENT_MASK               0x00000070
324 	#define DRV_STATUS_OEM_DISABLE_ENABLE_PF        0x00000010
325 	#define DRV_STATUS_OEM_BANDWIDTH_ALLOCATION     0x00000020
326 
327 	#define DRV_STATUS_OEM_UPDATE_SVID              0x00000080
328 
329 	#define DRV_STATUS_DCC_EVENT_MASK               0x0000ff00
330 	#define DRV_STATUS_DCC_DISABLE_ENABLE_PF        0x00000100
331 	#define DRV_STATUS_DCC_BANDWIDTH_ALLOCATION     0x00000200
332 	#define DRV_STATUS_DCC_CHANGE_MAC_ADDRESS       0x00000400
333 	#define DRV_STATUS_DCC_RESERVED1                0x00000800
334 	#define DRV_STATUS_DCC_SET_PROTOCOL             0x00001000
335 	#define DRV_STATUS_DCC_SET_PRIORITY             0x00002000
336 
337 	#define DRV_STATUS_DCBX_EVENT_MASK              0x000f0000
338 	#define DRV_STATUS_DCBX_NEGOTIATION_RESULTS     0x00010000
339 	#define DRV_STATUS_AFEX_EVENT_MASK              0x03f00000
340 	#define DRV_STATUS_AFEX_LISTGET_REQ             0x00100000
341 	#define DRV_STATUS_AFEX_LISTSET_REQ             0x00200000
342 	#define DRV_STATUS_AFEX_STATSGET_REQ            0x00400000
343 	#define DRV_STATUS_AFEX_VIFSET_REQ              0x00800000
344 
345 	#define DRV_STATUS_DRV_INFO_REQ                 0x04000000
346 
347 	#define DRV_STATUS_EEE_NEGOTIATION_RESULTS      0x08000000
348 
349 	u32 virt_mac_upper;
350 	#define VIRT_MAC_SIGN_MASK                      0xffff0000
351 	#define VIRT_MAC_SIGNATURE                      0x564d0000
352 	u32 virt_mac_lower;
353 
354 };
355 
356 
357 /****************************************************************************
358  * Management firmware state                                                *
359  ****************************************************************************/
360 /* Allocate 440 bytes for management firmware */
361 #define MGMTFW_STATE_WORD_SIZE                          110
362 
363 struct mgmtfw_state {
364 	u32 opaque[MGMTFW_STATE_WORD_SIZE];
365 };
366 
367 
368 /****************************************************************************
369  * Multi-Function configuration                                             *
370  ****************************************************************************/
371 struct shared_mf_cfg {
372 
373 	u32 clp_mb;
374 	#define SHARED_MF_CLP_SET_DEFAULT               0x00000000
375 	/* set by CLP */
376 	#define SHARED_MF_CLP_EXIT                      0x00000001
377 	/* set by MCP */
378 	#define SHARED_MF_CLP_EXIT_DONE                 0x00010000
379 
380 };
381 
382 struct port_mf_cfg {
383 
384 	u32 dynamic_cfg;    /* device control channel */
385 	#define PORT_MF_CFG_E1HOV_TAG_MASK              0x0000ffff
386 	#define PORT_MF_CFG_E1HOV_TAG_SHIFT             0
387 	#define PORT_MF_CFG_E1HOV_TAG_DEFAULT         PORT_MF_CFG_E1HOV_TAG_MASK
388 
389 	u32 reserved[1];
390 
391 };
392 
393 struct func_mf_cfg {
394 
395 	u32 config;
396 	/* E/R/I/D */
397 	/* function 0 of each port cannot be hidden */
398 	#define FUNC_MF_CFG_FUNC_HIDE                   0x00000001
399 
400 	#define FUNC_MF_CFG_PROTOCOL_MASK               0x00000006
401 	#define FUNC_MF_CFG_PROTOCOL_FCOE               0x00000000
402 	#define FUNC_MF_CFG_PROTOCOL_ETHERNET           0x00000002
403 	#define FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 0x00000004
404 	#define FUNC_MF_CFG_PROTOCOL_ISCSI              0x00000006
405 	#define FUNC_MF_CFG_PROTOCOL_DEFAULT \
406 				FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA
407 
408 	#define FUNC_MF_CFG_FUNC_DISABLED               0x00000008
409 	#define FUNC_MF_CFG_FUNC_DELETED                0x00000010
410 
411 	#define FUNC_MF_CFG_FUNC_BOOT_MASK              0x00000060
412 	#define FUNC_MF_CFG_FUNC_BOOT_BIOS_CTRL         0x00000000
413 	#define FUNC_MF_CFG_FUNC_BOOT_VCM_DISABLED      0x00000020
414 	#define FUNC_MF_CFG_FUNC_BOOT_VCM_ENABLED       0x00000040
415 
416 	/* PRI */
417 	/* 0 - low priority, 3 - high priority */
418 	#define FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK      0x00000300
419 	#define FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT     8
420 	#define FUNC_MF_CFG_TRANSMIT_PRIORITY_DEFAULT   0x00000000
421 
422 	/* MINBW, MAXBW */
423 	/* value range - 0..100, increments in 100Mbps */
424 	#define FUNC_MF_CFG_MIN_BW_MASK                 0x00ff0000
425 	#define FUNC_MF_CFG_MIN_BW_SHIFT                16
426 	#define FUNC_MF_CFG_MIN_BW_DEFAULT              0x00000000
427 	#define FUNC_MF_CFG_MAX_BW_MASK                 0xff000000
428 	#define FUNC_MF_CFG_MAX_BW_SHIFT                24
429 	#define FUNC_MF_CFG_MAX_BW_DEFAULT              0x64000000
430 
431 	u32 mac_upper;	    /* MAC */
432 	#define FUNC_MF_CFG_UPPERMAC_MASK               0x0000ffff
433 	#define FUNC_MF_CFG_UPPERMAC_SHIFT              0
434 	#define FUNC_MF_CFG_UPPERMAC_DEFAULT           FUNC_MF_CFG_UPPERMAC_MASK
435 	u32 mac_lower;
436 	#define FUNC_MF_CFG_LOWERMAC_DEFAULT            0xffffffff
437 
438 	u32 e1hov_tag;	/* VNI */
439 	#define FUNC_MF_CFG_E1HOV_TAG_MASK              0x0000ffff
440 	#define FUNC_MF_CFG_E1HOV_TAG_SHIFT             0
441 	#define FUNC_MF_CFG_E1HOV_TAG_DEFAULT         FUNC_MF_CFG_E1HOV_TAG_MASK
442 
443 	/* afex default VLAN ID - 12 bits */
444 	#define FUNC_MF_CFG_AFEX_VLAN_MASK              0x0fff0000
445 	#define FUNC_MF_CFG_AFEX_VLAN_SHIFT             16
446 
447 	u32 afex_config;
448 	#define FUNC_MF_CFG_AFEX_COS_FILTER_MASK                     0x000000ff
449 	#define FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT                    0
450 	#define FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK                    0x0000ff00
451 	#define FUNC_MF_CFG_AFEX_MBA_ENABLED_SHIFT                   8
452 	#define FUNC_MF_CFG_AFEX_MBA_ENABLED_VAL                     0x00000100
453 	#define FUNC_MF_CFG_AFEX_VLAN_MODE_MASK                      0x000f0000
454 	#define FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT                     16
455 
456 	u32 pf_allocation;
457 	/* number of vfs in function, if 0 - sriov disabled */
458 	#define FUNC_MF_CFG_NUMBER_OF_VFS_MASK                      0x000000FF
459 	#define FUNC_MF_CFG_NUMBER_OF_VFS_SHIFT                     0
460 };
461 
462 enum mf_cfg_afex_vlan_mode {
463 	FUNC_MF_CFG_AFEX_VLAN_TRUNK_MODE = 0,
464 	FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE,
465 	FUNC_MF_CFG_AFEX_VLAN_TRUNK_TAG_NATIVE_MODE
466 };
467 
468 /* This structure is not applicable and should not be accessed on 57711 */
469 struct func_ext_cfg {
470 	u32 func_cfg;
471 	#define MACP_FUNC_CFG_FLAGS_MASK                0x0000007F
472 	#define MACP_FUNC_CFG_FLAGS_SHIFT               0
473 	#define MACP_FUNC_CFG_FLAGS_ENABLED             0x00000001
474 	#define MACP_FUNC_CFG_FLAGS_ETHERNET            0x00000002
475 	#define MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD       0x00000004
476 	#define MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD        0x00000008
477     #define MACP_FUNC_CFG_PAUSE_ON_HOST_RING        0x00000080
478 
479 	u32 iscsi_mac_addr_upper;
480 	u32 iscsi_mac_addr_lower;
481 
482 	u32 fcoe_mac_addr_upper;
483 	u32 fcoe_mac_addr_lower;
484 
485 	u32 fcoe_wwn_port_name_upper;
486 	u32 fcoe_wwn_port_name_lower;
487 
488 	u32 fcoe_wwn_node_name_upper;
489 	u32 fcoe_wwn_node_name_lower;
490 
491 	u32 preserve_data;
492 	#define MF_FUNC_CFG_PRESERVE_L2_MAC             (1<<0)
493 	#define MF_FUNC_CFG_PRESERVE_ISCSI_MAC          (1<<1)
494 	#define MF_FUNC_CFG_PRESERVE_FCOE_MAC           (1<<2)
495 	#define MF_FUNC_CFG_PRESERVE_FCOE_WWN_P         (1<<3)
496 	#define MF_FUNC_CFG_PRESERVE_FCOE_WWN_N         (1<<4)
497 	#define MF_FUNC_CFG_PRESERVE_TX_BW              (1<<5)
498 };
499 
500 struct mf_cfg {
501 
502 	struct shared_mf_cfg    shared_mf_config;       /* 0x4 */
503 	struct port_mf_cfg  port_mf_config[NVM_PATH_MAX][PORT_MAX];
504     /* 0x10*2=0x20 */
505 	/* for all chips, there are 8 mf functions */
506 	struct func_mf_cfg  func_mf_config[E1H_FUNC_MAX]; /* 0x18 * 8 = 0xc0 */
507 	/*
508 	 * Extended configuration per function  - this array does not exist and
509 	 * should not be accessed on 57711
510 	 */
511 	struct func_ext_cfg func_ext_config[E1H_FUNC_MAX]; /* 0x28 * 8 = 0x140*/
512 }; /* 0x224 */
513 
514 /****************************************************************************
515  * Shared Memory Region                                                     *
516  ****************************************************************************/
517 struct shmem_region {		       /*   SharedMem Offset (size) */
518 
519 	u32         validity_map[PORT_MAX];  /* 0x0 (4*2 = 0x8) */
520 	#define SHR_MEM_FORMAT_REV_MASK                     0xff000000
521 	#define SHR_MEM_FORMAT_REV_ID                       ('A'<<24)
522 	/* validity bits */
523 	#define SHR_MEM_VALIDITY_PCI_CFG                    0x00100000
524 	#define SHR_MEM_VALIDITY_MB                         0x00200000
525 	#define SHR_MEM_VALIDITY_DEV_INFO                   0x00400000
526 	#define SHR_MEM_VALIDITY_RESERVED                   0x00000007
527 	/* One licensing bit should be set */
528 	#define SHR_MEM_VALIDITY_LIC_KEY_IN_EFFECT_MASK     0x00000038
529 	#define SHR_MEM_VALIDITY_LIC_MANUF_KEY_IN_EFFECT    0x00000008
530 	#define SHR_MEM_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT  0x00000010
531 	#define SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT       0x00000020
532 	/* Active MFW */
533 	#define SHR_MEM_VALIDITY_ACTIVE_MFW_UNKNOWN         0x00000000
534 	#define SHR_MEM_VALIDITY_ACTIVE_MFW_MASK            0x000001c0
535 	#define SHR_MEM_VALIDITY_ACTIVE_MFW_IPMI            0x00000040
536 	#define SHR_MEM_VALIDITY_ACTIVE_MFW_UMP             0x00000080
537 	#define SHR_MEM_VALIDITY_ACTIVE_MFW_NCSI            0x000000c0
538 	#define SHR_MEM_VALIDITY_ACTIVE_MFW_NONE            0x000001c0
539 
540 	struct shm_dev_info dev_info;	     /* 0x8     (0x438) */
541 
542 	license_key_t       drv_lic_key[PORT_MAX]; /* 0x440 (52*2=0x68) */
543 
544 	/* FW information (for internal FW use) */
545 	u32         fw_info_fio_offset;		/* 0x4a8       (0x4) */
546 	struct mgmtfw_state mgmtfw_state;	/* 0x4ac     (0x1b8) */
547 
548 	struct drv_port_mb  port_mb[PORT_MAX];	/* 0x664 (16*2=0x20) */
549 
550 
551 #ifdef BMAPI
552 	/* This is a variable length array */
553 	/* the number of function depends on the chip type */
554 	struct drv_func_mb func_mb[1];	/* 0x684 (44*2/4/8=0x58/0xb0/0x160) */
555 #else
556 	/* the number of function depends on the chip type */
557 	struct drv_func_mb  func_mb[];	/* 0x684 (44*2/4/8=0x58/0xb0/0x160) */
558 #endif /* BMAPI */
559 
560 }; /* 57710 = 0x6dc | 57711 = 0x7E4 | 57712 = 0x734 */
561 
562 /****************************************************************************
563  * Shared Memory 2 Region                                                   *
564  ****************************************************************************/
565 /* The fw_flr_ack is actually built in the following way:                   */
566 /* 8 bit:  PF ack                                                           */
567 /* 64 bit: VF ack                                                           */
568 /* 8 bit:  ios_dis_ack                                                      */
569 /* In order to maintain endianity in the mailbox hsi, we want to keep using */
570 /* u32. The fw must have the VF right after the PF since this is how it     */
571 /* access arrays(it expects always the VF to reside after the PF, and that  */
572 /* makes the calculation much easier for it. )                              */
573 /* In order to answer both limitations, and keep the struct small, the code */
574 /* will abuse the structure defined here to achieve the actual partition    */
575 /* above                                                                    */
576 /****************************************************************************/
577 struct fw_flr_ack {
578 	u32         pf_ack;
579 	u32         vf_ack;
580 	u32         iov_dis_ack;
581 };
582 
583 struct fw_flr_mb {
584 	u32         aggint;
585 	u32         opgen_addr;
586 	struct fw_flr_ack ack;
587 };
588 
589 struct eee_remote_vals {
590 	u32         tx_tw;
591 	u32         rx_tw;
592 };
593 
594 /**** SUPPORT FOR SHMEM ARRRAYS ***
595  * The SHMEM HSI is aligned on 32 bit boundaries which makes it difficult to
596  * define arrays with storage types smaller then unsigned dwords.
597  * The macros below add generic support for SHMEM arrays with numeric elements
598  * that can span 2,4,8 or 16 bits. The array underlying type is a 32 bit dword
599  * array with individual bit-filed elements accessed using shifts and masks.
600  *
601  */
602 
603 /* eb is the bitwidth of a single element */
604 #define SHMEM_ARRAY_MASK(eb)		((1<<(eb))-1)
605 #define SHMEM_ARRAY_ENTRY(i, eb)	((i)/(32/(eb)))
606 
607 /* the bit-position macro allows the used to flip the order of the arrays
608  * elements on a per byte or word boundary.
609  *
610  * example: an array with 8 entries each 4 bit wide. This array will fit into
611  * a single dword. The diagrmas below show the array order of the nibbles.
612  *
613  * SHMEM_ARRAY_BITPOS(i, 4, 4) defines the stadard ordering:
614  *
615  *                |                |                |               |
616  *   0    |   1   |   2    |   3   |   4    |   5   |   6   |   7   |
617  *                |                |                |               |
618  *
619  * SHMEM_ARRAY_BITPOS(i, 4, 8) defines a flip ordering per byte:
620  *
621  *                |                |                |               |
622  *   1   |   0    |   3    |   2   |   5    |   4   |   7   |   6   |
623  *                |                |                |               |
624  *
625  * SHMEM_ARRAY_BITPOS(i, 4, 16) defines a flip ordering per word:
626  *
627  *                |                |                |               |
628  *   3   |   2    |   1   |   0    |   7   |   6    |   5   |   4   |
629  *                |                |                |               |
630  */
631 #define SHMEM_ARRAY_BITPOS(i, eb, fb)	\
632 	((((32/(fb)) - 1 - ((i)/((fb)/(eb))) % (32/(fb))) * (fb)) + \
633 	(((i)%((fb)/(eb))) * (eb)))
634 
635 #define SHMEM_ARRAY_GET(a, i, eb, fb)					\
636 	((a[SHMEM_ARRAY_ENTRY(i, eb)] >> SHMEM_ARRAY_BITPOS(i, eb, fb)) &  \
637 	SHMEM_ARRAY_MASK(eb))
638 
639 #define SHMEM_ARRAY_SET(a, i, eb, fb, val)				\
640 do {									   \
641 	a[SHMEM_ARRAY_ENTRY(i, eb)] &= ~(SHMEM_ARRAY_MASK(eb) <<	   \
642 	SHMEM_ARRAY_BITPOS(i, eb, fb));					   \
643 	a[SHMEM_ARRAY_ENTRY(i, eb)] |= (((val) & SHMEM_ARRAY_MASK(eb)) <<  \
644 	SHMEM_ARRAY_BITPOS(i, eb, fb));					   \
645 } while (0)
646 
647 
648 
649 /****START OF DCBX STRUCTURES DECLARATIONS****/
650 #define DCBX_MAX_NUM_PRI_PG_ENTRIES	8
651 #define DCBX_PRI_PG_BITWIDTH		4
652 #define DCBX_PRI_PG_FBITS		8
653 #define DCBX_PRI_PG_GET(a, i)		\
654 	SHMEM_ARRAY_GET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS)
655 #define DCBX_PRI_PG_SET(a, i, val)	\
656 	SHMEM_ARRAY_SET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS, val)
657 #define DCBX_MAX_NUM_PG_BW_ENTRIES	8
658 #define DCBX_BW_PG_BITWIDTH		8
659 #define DCBX_PG_BW_GET(a, i)		\
660 	SHMEM_ARRAY_GET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH)
661 #define DCBX_PG_BW_SET(a, i, val)	\
662 	SHMEM_ARRAY_SET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH, val)
663 #define DCBX_STRICT_PRI_PG		15
664 #define DCBX_MAX_APP_PROTOCOL		16
665 #define DCBX_MAX_APP_LOCAL	    32
666 #define FCOE_APP_IDX			0
667 #define ISCSI_APP_IDX			1
668 #define PREDEFINED_APP_IDX_MAX		2
669 
670 
671 /* Big/Little endian have the same representation. */
672 struct dcbx_ets_feature {
673 	/*
674 	 * For Admin MIB - is this feature supported by the
675 	 * driver | For Local MIB - should this feature be enabled.
676 	 */
677 	u32 enabled;
678 	u32  pg_bw_tbl[2];
679 	u32  pri_pg_tbl[1];
680 };
681 
682 /* Driver structure in LE */
683 struct dcbx_pfc_feature {
684 #ifdef __BIG_ENDIAN
685 	u8 pri_en_bitmap;
686 	#define DCBX_PFC_PRI_0 0x01
687 	#define DCBX_PFC_PRI_1 0x02
688 	#define DCBX_PFC_PRI_2 0x04
689 	#define DCBX_PFC_PRI_3 0x08
690 	#define DCBX_PFC_PRI_4 0x10
691 	#define DCBX_PFC_PRI_5 0x20
692 	#define DCBX_PFC_PRI_6 0x40
693 	#define DCBX_PFC_PRI_7 0x80
694 	u8 pfc_caps;
695 	u8 reserved;
696 	u8 enabled;
697 #elif defined(__LITTLE_ENDIAN)
698 	u8 enabled;
699 	u8 reserved;
700 	u8 pfc_caps;
701 	u8 pri_en_bitmap;
702 	#define DCBX_PFC_PRI_0 0x01
703 	#define DCBX_PFC_PRI_1 0x02
704 	#define DCBX_PFC_PRI_2 0x04
705 	#define DCBX_PFC_PRI_3 0x08
706 	#define DCBX_PFC_PRI_4 0x10
707 	#define DCBX_PFC_PRI_5 0x20
708 	#define DCBX_PFC_PRI_6 0x40
709 	#define DCBX_PFC_PRI_7 0x80
710 #endif
711 };
712 
713 struct dcbx_app_priority_entry {
714 #ifdef __BIG_ENDIAN
715 	u16  app_id;
716 	u8  pri_bitmap;
717 	u8  appBitfield;
718 	#define DCBX_APP_ENTRY_VALID         0x01
719 	#define DCBX_APP_ENTRY_SF_MASK       0x30
720 	#define DCBX_APP_ENTRY_SF_SHIFT      4
721 	#define DCBX_APP_SF_ETH_TYPE         0x10
722 	#define DCBX_APP_SF_PORT             0x20
723 	#define DCBX_APP_PRI_0               0x01
724 	#define DCBX_APP_PRI_1               0x02
725 	#define DCBX_APP_PRI_2               0x04
726 	#define DCBX_APP_PRI_3               0x08
727 	#define DCBX_APP_PRI_4               0x10
728 	#define DCBX_APP_PRI_5               0x20
729 	#define DCBX_APP_PRI_6               0x40
730 	#define DCBX_APP_PRI_7               0x80
731 #elif defined(__LITTLE_ENDIAN)
732 	u8 appBitfield;
733 	#define DCBX_APP_ENTRY_VALID         0x01
734 	#define DCBX_APP_ENTRY_SF_MASK       0x30
735 	#define DCBX_APP_ENTRY_SF_SHIFT      4
736 	#define DCBX_APP_SF_ETH_TYPE         0x10
737 	#define DCBX_APP_SF_PORT             0x20
738 	u8  pri_bitmap;
739 	u16  app_id;
740 #endif
741 };
742 
743 
744 /* FW structure in BE */
745 struct dcbx_app_priority_feature {
746 #ifdef __BIG_ENDIAN
747 	u8 reserved;
748 	u8 default_pri;
749 	u8 tc_supported;
750 	u8 enabled;
751 #elif defined(__LITTLE_ENDIAN)
752 	u8 enabled;
753 	u8 tc_supported;
754 	u8 default_pri;
755 	u8 reserved;
756 #endif
757 	struct dcbx_app_priority_entry  app_pri_tbl[DCBX_MAX_APP_PROTOCOL];
758 };
759 
760 /* FW structure in BE */
761 struct dcbx_features {
762 	/* PG feature */
763 	struct dcbx_ets_feature ets;
764 	/* PFC feature */
765 	struct dcbx_pfc_feature pfc;
766 	/* APP feature */
767 	struct dcbx_app_priority_feature app;
768 };
769 
770 /* LLDP protocol parameters */
771 /* FW structure in BE */
772 struct lldp_params {
773 #ifdef __BIG_ENDIAN
774 	u8  msg_fast_tx_interval;
775 	u8  msg_tx_hold;
776 	u8  msg_tx_interval;
777 	u8  admin_status;
778 	#define LLDP_TX_ONLY  0x01
779 	#define LLDP_RX_ONLY  0x02
780 	#define LLDP_TX_RX    0x03
781 	#define LLDP_DISABLED 0x04
782 	u8  reserved1;
783 	u8  tx_fast;
784 	u8  tx_crd_max;
785 	u8  tx_crd;
786 #elif defined(__LITTLE_ENDIAN)
787 	u8  admin_status;
788 	#define LLDP_TX_ONLY  0x01
789 	#define LLDP_RX_ONLY  0x02
790 	#define LLDP_TX_RX    0x03
791 	#define LLDP_DISABLED 0x04
792 	u8  msg_tx_interval;
793 	u8  msg_tx_hold;
794 	u8  msg_fast_tx_interval;
795 	u8  tx_crd;
796 	u8  tx_crd_max;
797 	u8  tx_fast;
798 	u8  reserved1;
799 #endif
800 	#define REM_CHASSIS_ID_STAT_LEN 4
801 	#define REM_PORT_ID_STAT_LEN 4
802 	/* Holds remote Chassis ID TLV header, subtype and 9B of payload. */
803 	u32 peer_chassis_id[REM_CHASSIS_ID_STAT_LEN];
804 	/* Holds remote Port ID TLV header, subtype and 9B of payload. */
805 	u32 peer_port_id[REM_PORT_ID_STAT_LEN];
806 };
807 
808 struct lldp_dcbx_stat {
809 	#define LOCAL_CHASSIS_ID_STAT_LEN 2
810 	#define LOCAL_PORT_ID_STAT_LEN 2
811 	/* Holds local Chassis ID 8B payload of constant subtype 4. */
812 	u32 local_chassis_id[LOCAL_CHASSIS_ID_STAT_LEN];
813 	/* Holds local Port ID 8B payload of constant subtype 3. */
814 	u32 local_port_id[LOCAL_PORT_ID_STAT_LEN];
815 	/* Number of DCBX frames transmitted. */
816 	u32 num_tx_dcbx_pkts;
817 	/* Number of DCBX frames received. */
818 	u32 num_rx_dcbx_pkts;
819 };
820 
821 /* ADMIN MIB - DCBX local machine default configuration. */
822 struct lldp_admin_mib {
823 	u32     ver_cfg_flags;
824 	#define DCBX_ETS_CONFIG_TX_ENABLED       0x00000001
825 	#define DCBX_PFC_CONFIG_TX_ENABLED       0x00000002
826 	#define DCBX_APP_CONFIG_TX_ENABLED       0x00000004
827 	#define DCBX_ETS_RECO_TX_ENABLED         0x00000008
828 	#define DCBX_ETS_RECO_VALID              0x00000010
829 	#define DCBX_ETS_WILLING                 0x00000020
830 	#define DCBX_PFC_WILLING                 0x00000040
831 	#define DCBX_APP_WILLING                 0x00000080
832 	#define DCBX_VERSION_CEE                 0x00000100
833 	#define DCBX_VERSION_IEEE                0x00000200
834 	#define DCBX_DCBX_ENABLED                0x00000400
835 	#define DCBX_CEE_VERSION_MASK            0x0000f000
836 	#define DCBX_CEE_VERSION_SHIFT           12
837 	#define DCBX_CEE_MAX_VERSION_MASK        0x000f0000
838 	#define DCBX_CEE_MAX_VERSION_SHIFT       16
839 	struct dcbx_features     features;
840 };
841 
842 /* REMOTE MIB - remote machine DCBX configuration. */
843 struct lldp_remote_mib {
844 	u32 prefix_seq_num;
845 	u32 flags;
846 	#define DCBX_ETS_TLV_RX                  0x00000001
847 	#define DCBX_PFC_TLV_RX                  0x00000002
848 	#define DCBX_APP_TLV_RX                  0x00000004
849 	#define DCBX_ETS_RX_ERROR                0x00000010
850 	#define DCBX_PFC_RX_ERROR                0x00000020
851 	#define DCBX_APP_RX_ERROR                0x00000040
852 	#define DCBX_ETS_REM_WILLING             0x00000100
853 	#define DCBX_PFC_REM_WILLING             0x00000200
854 	#define DCBX_APP_REM_WILLING             0x00000400
855 	#define DCBX_REMOTE_ETS_RECO_VALID       0x00001000
856 	#define DCBX_REMOTE_MIB_VALID            0x00002000
857 	struct dcbx_features features;
858 	u32 suffix_seq_num;
859 };
860 
861 /* LOCAL MIB - operational DCBX configuration - transmitted on Tx LLDPDU. */
862 struct lldp_local_mib {
863 	u32 prefix_seq_num;
864 	/* Indicates if there is mismatch with negotiation results. */
865 	u32 error;
866 	#define DCBX_LOCAL_ETS_ERROR             0x00000001
867 	#define DCBX_LOCAL_PFC_ERROR             0x00000002
868 	#define DCBX_LOCAL_APP_ERROR             0x00000004
869 	#define DCBX_LOCAL_PFC_MISMATCH          0x00000010
870 	#define DCBX_LOCAL_APP_MISMATCH          0x00000020
871 	#define DCBX_REMOTE_MIB_ERROR            0x00000040
872 	#define DCBX_REMOTE_ETS_TLV_NOT_FOUND    0x00000080
873 	#define DCBX_REMOTE_PFC_TLV_NOT_FOUND    0x00000100
874 	#define DCBX_REMOTE_APP_TLV_NOT_FOUND    0x00000200
875 	struct dcbx_features   features;
876 	u32 suffix_seq_num;
877 };
878 
879 struct lldp_local_mib_ext {
880 	u32 prefix_seq_num;
881 	/* APP TLV extension - 16 more entries for negotiation results*/
882 	struct dcbx_app_priority_entry  app_pri_tbl_ext[DCBX_MAX_APP_PROTOCOL];
883 	u32 suffix_seq_num;
884 };
885 /***END OF DCBX STRUCTURES DECLARATIONS***/
886 
887 /***********************************************************/
888 /*                         Elink section                   */
889 /***********************************************************/
890 #define SHMEM_LINK_CONFIG_SIZE 2
891 struct shmem_lfa {
892 	u32 req_duplex;
893 	#define REQ_DUPLEX_PHY0_MASK        0x0000ffff
894 	#define REQ_DUPLEX_PHY0_SHIFT       0
895 	#define REQ_DUPLEX_PHY1_MASK        0xffff0000
896 	#define REQ_DUPLEX_PHY1_SHIFT       16
897 	u32 req_flow_ctrl;
898 	#define REQ_FLOW_CTRL_PHY0_MASK     0x0000ffff
899 	#define REQ_FLOW_CTRL_PHY0_SHIFT    0
900 	#define REQ_FLOW_CTRL_PHY1_MASK     0xffff0000
901 	#define REQ_FLOW_CTRL_PHY1_SHIFT    16
902 	u32 req_line_speed; /* Also determine AutoNeg */
903 	#define REQ_LINE_SPD_PHY0_MASK      0x0000ffff
904 	#define REQ_LINE_SPD_PHY0_SHIFT     0
905 	#define REQ_LINE_SPD_PHY1_MASK      0xffff0000
906 	#define REQ_LINE_SPD_PHY1_SHIFT     16
907 	u32 speed_cap_mask[SHMEM_LINK_CONFIG_SIZE];
908 	u32 additional_config;
909 	#define REQ_FC_AUTO_ADV_MASK        0x0000ffff
910 	#define REQ_FC_AUTO_ADV0_SHIFT      0
911 	#define NO_LFA_DUE_TO_DCC_MASK      0x00010000
912 	u32 lfa_sts;
913 	#define LFA_LINK_FLAP_REASON_OFFSET		0
914 	#define LFA_LINK_FLAP_REASON_MASK		0x000000ff
915 		#define LFA_LINK_DOWN			    0x1
916 		#define LFA_LOOPBACK_ENABLED		0x2
917 		#define LFA_DUPLEX_MISMATCH		    0x3
918 		#define LFA_MFW_IS_TOO_OLD		    0x4
919 		#define LFA_LINK_SPEED_MISMATCH		0x5
920 		#define LFA_FLOW_CTRL_MISMATCH		0x6
921 		#define LFA_SPEED_CAP_MISMATCH		0x7
922 		#define LFA_DCC_LFA_DISABLED		0x8
923 		#define LFA_EEE_MISMATCH		0x9
924 
925 	#define LINK_FLAP_AVOIDANCE_COUNT_OFFSET	8
926 	#define LINK_FLAP_AVOIDANCE_COUNT_MASK		0x0000ff00
927 
928 	#define LINK_FLAP_COUNT_OFFSET			16
929 	#define LINK_FLAP_COUNT_MASK			0x00ff0000
930 
931 	#define LFA_FLAGS_MASK				0xff000000
932 	#define SHMEM_LFA_DONT_CLEAR_STAT		(1<<24)
933 
934 };
935 
936 /*
937 Used to suppoert NSCI get OS driver version
938 On driver load the version value will be set
939 On driver unload driver value of 0x0 will be set
940 */
941 struct os_drv_ver{
942 	#define DRV_VER_NOT_LOADED                      0
943 	/*personalites orrder is importent */
944 	#define DRV_PERS_ETHERNET                       0
945 	#define DRV_PERS_ISCSI                          1
946 	#define DRV_PERS_FCOE                           2
947 	/*shmem2 struct is constatnt can't add more personalites here*/
948 	#define MAX_DRV_PERS                            3
949 	u32  versions[MAX_DRV_PERS];
950 };
951 
952 struct shmem2_region {
953 
954 	u32 size;					/* 0x0000 */
955 
956 	u32 dcc_support;				/* 0x0004 */
957 	#define SHMEM_DCC_SUPPORT_NONE                      0x00000000
958 	#define SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV     0x00000001
959 	#define SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV  0x00000004
960 	#define SHMEM_DCC_SUPPORT_CHANGE_MAC_ADDRESS_TLV    0x00000008
961 	#define SHMEM_DCC_SUPPORT_SET_PROTOCOL_TLV          0x00000040
962 	#define SHMEM_DCC_SUPPORT_SET_PRIORITY_TLV          0x00000080
963 
964 	u32 ext_phy_fw_version2[PORT_MAX];		/* 0x0008 */
965 	/*
966 	 * For backwards compatibility, if the mf_cfg_addr does not exist
967 	 * (the size filed is smaller than 0xc) the mf_cfg resides at the
968 	 * end of struct shmem_region
969 	 */
970 	u32 mf_cfg_addr;				/* 0x0010 */
971 	#define SHMEM_MF_CFG_ADDR_NONE                  0x00000000
972 
973 	struct fw_flr_mb flr_mb;			/* 0x0014 */
974 	u32 dcbx_lldp_params_offset;			/* 0x0028 */
975 	#define SHMEM_LLDP_DCBX_PARAMS_NONE             0x00000000
976 	u32 dcbx_neg_res_offset;			/* 0x002c */
977 	#define SHMEM_DCBX_NEG_RES_NONE			0x00000000
978 	u32 dcbx_remote_mib_offset;			/* 0x0030 */
979 	#define SHMEM_DCBX_REMOTE_MIB_NONE              0x00000000
980 	/*
981 	 * The other shmemX_base_addr holds the other path's shmem address
982 	 * required for example in case of common phy init, or for path1 to know
983 	 * the address of mcp debug trace which is located in offset from shmem
984 	 * of path0
985 	 */
986 	u32 other_shmem_base_addr;			/* 0x0034 */
987 	u32 other_shmem2_base_addr;			/* 0x0038 */
988 	/*
989 	 * mcp_vf_disabled is set by the MCP to indicate the driver about VFs
990 	 * which were disabled/flred
991 	 */
992 	u32 mcp_vf_disabled[E2_VF_MAX / 32];		/* 0x003c */
993 
994 	/*
995 	 * drv_ack_vf_disabled is set by the PF driver to ack handled disabled
996 	 * VFs
997 	 */
998 	u32 drv_ack_vf_disabled[E2_FUNC_MAX][E2_VF_MAX / 32]; /* 0x0044 */
999 
1000 	u32 dcbx_lldp_dcbx_stat_offset;			/* 0x0064 */
1001 	#define SHMEM_LLDP_DCBX_STAT_NONE               0x00000000
1002 
1003 	/*
1004 	 * edebug_driver_if field is used to transfer messages between edebug
1005 	 * app to the driver through shmem2.
1006 	 *
1007 	 * message format:
1008 	 * bits 0-2 -  function number / instance of driver to perform request
1009 	 * bits 3-5 -  op code / is_ack?
1010 	 * bits 6-63 - data
1011 	 */
1012 	u32 edebug_driver_if[2];			/* 0x0068 */
1013 	#define EDEBUG_DRIVER_IF_OP_CODE_GET_PHYS_ADDR  1
1014 	#define EDEBUG_DRIVER_IF_OP_CODE_GET_BUS_ADDR   2
1015 	#define EDEBUG_DRIVER_IF_OP_CODE_DISABLE_STAT   3
1016 
1017 	u32 nvm_retain_bitmap_addr;			/* 0x0070 */
1018 
1019 	/* afex support of that driver */
1020 	u32 afex_driver_support;			/* 0x0074 */
1021 	#define SHMEM_AFEX_VERSION_MASK                  0x100f
1022 	#define SHMEM_AFEX_SUPPORTED_VERSION_ONE         0x1001
1023 	#define SHMEM_AFEX_REDUCED_DRV_LOADED            0x8000
1024 
1025 	/* driver receives addr in scratchpad to which it should respond */
1026 	u32 afex_scratchpad_addr_to_write[E2_FUNC_MAX];
1027 
1028 	/*
1029 	 * generic params from MCP to driver (value depends on the msg sent
1030 	 * to driver
1031 	 */
1032 	u32 afex_param1_to_driver[E2_FUNC_MAX];		/* 0x0088 */
1033 	u32 afex_param2_to_driver[E2_FUNC_MAX];		/* 0x0098 */
1034 
1035 	u32 swim_base_addr;				/* 0x0108 */
1036 	u32 swim_funcs;
1037 	u32 swim_main_cb;
1038 
1039 	/*
1040 	 * bitmap notifying which VIF profiles stored in nvram are enabled by
1041 	 * switch
1042 	 */
1043 	u32 afex_profiles_enabled[2];
1044 
1045 	/* generic flags controlled by the driver */
1046 	u32 drv_flags;
1047 	#define DRV_FLAGS_DCB_CONFIGURED		0x0
1048 	#define DRV_FLAGS_DCB_CONFIGURATION_ABORTED	0x1
1049 	#define DRV_FLAGS_DCB_MFW_CONFIGURED	0x2
1050 
1051     #define DRV_FLAGS_PORT_MASK	((1 << DRV_FLAGS_DCB_CONFIGURED) | \
1052 			(1 << DRV_FLAGS_DCB_CONFIGURATION_ABORTED) | \
1053 			(1 << DRV_FLAGS_DCB_MFW_CONFIGURED))
1054 	/* Port offset*/
1055 	#define DRV_FLAGS_P0_OFFSET		0
1056 	#define DRV_FLAGS_P1_OFFSET		16
1057 	#define DRV_FLAGS_GET_PORT_OFFSET(_port)	((0 == _port) ? \
1058 						DRV_FLAGS_P0_OFFSET : \
1059 						DRV_FLAGS_P1_OFFSET)
1060 
1061 	#define DRV_FLAGS_GET_PORT_MASK(_port)	(DRV_FLAGS_PORT_MASK << \
1062 	DRV_FLAGS_GET_PORT_OFFSET(_port))
1063 
1064 	#define DRV_FLAGS_FILED_BY_PORT(_field_bit, _port)	(1 << ( \
1065 	(_field_bit) + DRV_FLAGS_GET_PORT_OFFSET(_port)))
1066 
1067 	/* pointer to extended dev_info shared data copied from nvm image */
1068 	u32 extended_dev_info_shared_addr;
1069 	u32 ncsi_oem_data_addr;
1070 
1071 	u32 sensor_data_addr;
1072 	u32 buffer_block_addr;
1073 	u32 sensor_data_req_update_interval;
1074 	u32 temperature_in_half_celsius;
1075 	u32 glob_struct_in_host;
1076 
1077 	u32 dcbx_neg_res_ext_offset;
1078 	#define SHMEM_DCBX_NEG_RES_EXT_NONE			0x00000000
1079 
1080 	u32 drv_capabilities_flag[E2_FUNC_MAX];
1081 	#define DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED 0x00000001
1082 	#define DRV_FLAGS_CAPABILITIES_LOADED_L2        0x00000002
1083 	#define DRV_FLAGS_CAPABILITIES_LOADED_FCOE      0x00000004
1084 	#define DRV_FLAGS_CAPABILITIES_LOADED_ISCSI     0x00000008
1085 	#define DRV_FLAGS_MTU_MASK			0xffff0000
1086 	#define DRV_FLAGS_MTU_SHIFT				16
1087 
1088 	u32 extended_dev_info_shared_cfg_size;
1089 
1090 	u32 dcbx_en[PORT_MAX];
1091 
1092 	/* The offset points to the multi threaded meta structure */
1093 	u32 multi_thread_data_offset;
1094 
1095 	/* address of DMAable host address holding values from the drivers */
1096 	u32 drv_info_host_addr_lo;
1097 	u32 drv_info_host_addr_hi;
1098 
1099 	/* general values written by the MFW (such as current version) */
1100 	u32 drv_info_control;
1101 	#define DRV_INFO_CONTROL_VER_MASK          0x000000ff
1102 	#define DRV_INFO_CONTROL_VER_SHIFT         0
1103 	#define DRV_INFO_CONTROL_OP_CODE_MASK      0x0000ff00
1104 	#define DRV_INFO_CONTROL_OP_CODE_SHIFT     8
1105 	u32 ibft_host_addr; /* initialized by option ROM */
1106 
1107 	struct eee_remote_vals eee_remote_vals[PORT_MAX];
1108 	u32 pf_allocation[E2_FUNC_MAX];
1109 	#define PF_ALLOACTION_MSIX_VECTORS_MASK    0x000000ff /* real value, as PCI config space can show only maximum of 64 vectors */
1110 	#define PF_ALLOACTION_MSIX_VECTORS_SHIFT   0
1111 
1112 	/* the status of EEE auto-negotiation
1113 	 * bits 15:0 the configured tx-lpi entry timer value. Depends on bit 31.
1114 	 * bits 19:16 the supported modes for EEE.
1115 	 * bits 23:20 the speeds advertised for EEE.
1116 	 * bits 27:24 the speeds the Link partner advertised for EEE.
1117 	 * The supported/adv. modes in bits 27:19 originate from the
1118 	 * SHMEM_EEE_XXX_ADV definitions (where XXX is replaced by speed).
1119 	 * bit 28 when 1'b1 EEE was requested.
1120 	 * bit 29 when 1'b1 tx lpi was requested.
1121 	 * bit 30 when 1'b1 EEE was negotiated. Tx lpi will be asserted iff
1122 	 * 30:29 are 2'b11.
1123 	 * bit 31 when 1'b0 bits 15:0 contain a PORT_FEAT_CFG_EEE_ define as
1124 	 * value. When 1'b1 those bits contains a value times 16 microseconds.
1125 	 */
1126 	u32 eee_status[PORT_MAX];
1127 	#define SHMEM_EEE_TIMER_MASK		   0x0000ffff
1128 	#define SHMEM_EEE_SUPPORTED_MASK	   0x000f0000
1129 	#define SHMEM_EEE_SUPPORTED_SHIFT	   16
1130 	#define SHMEM_EEE_ADV_STATUS_MASK	   0x00f00000
1131 		#define SHMEM_EEE_100M_ADV	   (1U<<0)
1132 		#define SHMEM_EEE_1G_ADV	   (1U<<1)
1133 		#define SHMEM_EEE_10G_ADV	   (1U<<2)
1134 	#define SHMEM_EEE_ADV_STATUS_SHIFT	   20
1135 	#define	SHMEM_EEE_LP_ADV_STATUS_MASK	   0x0f000000
1136 	#define SHMEM_EEE_LP_ADV_STATUS_SHIFT	   24
1137 	#define SHMEM_EEE_REQUESTED_BIT		   0x10000000
1138 	#define SHMEM_EEE_LPI_REQUESTED_BIT	   0x20000000
1139 	#define SHMEM_EEE_ACTIVE_BIT		   0x40000000
1140 	#define SHMEM_EEE_TIME_OUTPUT_BIT	   0x80000000
1141 
1142 	u32 sizeof_port_stats;
1143 
1144 	/* Link Flap Avoidance */
1145 	u32 lfa_host_addr[PORT_MAX];
1146 
1147     /* External PHY temperature in deg C. */
1148 	u32 extphy_temps_in_celsius;
1149 	#define EXTPHY1_TEMP_MASK                  0x0000ffff
1150 	#define EXTPHY1_TEMP_SHIFT                 0
1151 
1152 	u32 ocdata_info_addr;			/* Offset 0x148 */
1153 	u32 drv_func_info_addr;			/* Offset 0x14C */
1154 	u32 drv_func_info_size;			/* Offset 0x150 */
1155 	u32 link_attr_sync[PORT_MAX];		/* Offset 0x154 */
1156 	#define LINK_ATTR_SYNC_KR2_ENABLE	0x00000001
1157 	#define LINK_SFP_EEPROM_COMP_CODE_MASK	0x0000ff00
1158 	#define LINK_SFP_EEPROM_COMP_CODE_SHIFT		 8
1159 	#define LINK_SFP_EEPROM_COMP_CODE_SR	0x00001000
1160 	#define LINK_SFP_EEPROM_COMP_CODE_LR	0x00002000
1161 	#define LINK_SFP_EEPROM_COMP_CODE_LRM	0x00004000
1162 
1163 	u32 ibft_host_addr_hi;  /* Initialize by uEFI ROM Offset 0x158 */
1164 	u32 fcode_ver;                          /* Offset 0x15c */
1165 	u32 link_change_count[PORT_MAX];        /* Offset 0x160-0x164 */
1166 	#define LINK_CHANGE_COUNT_MASK 0xff     /* Offset 0x168 */
1167         /* driver version for each personality*/
1168         struct os_drv_ver func_os_drv_ver[E2_FUNC_MAX]; /* Offset 0x16c */
1169 
1170 	/* Flag to the driver that PF's drv_info_host_addr buffer was read  */
1171 	u32 mfw_drv_indication;
1172 
1173 	/* We use inidcation for each PF (0..3) */
1174 	#define MFW_DRV_IND_READ_DONE_OFFSET(_pf_)  (1 << _pf_)
1175 };
1176 
1177 #endif
1178