1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2009-2015 QLogic Corporation. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 /* 28 * Copyright (c) 2008, 2015, Oracle and/or its affiliates. All rights reserved. 29 */ 30 31 #ifndef _QLT_REGS_H 32 #define _QLT_REGS_H 33 34 #include <sys/stmf_defines.h> 35 36 #ifdef __cplusplus 37 extern "C" { 38 #endif 39 40 /* 41 * Register offsets 42 */ 43 #define REG_FLASH_ADDR 0x00 44 #define REG_FLASH_DATA 0x04 45 #define REG_CTRL_STATUS 0x08 46 #define REG_INTR_CTRL 0x0C 47 #define REG_INTR_STATUS 0x10 48 49 #define REG_REQ_IN_PTR 0x1C 50 #define REG_REQ_OUT_PTR 0x20 51 #define REG_RESP_IN_PTR 0x24 52 #define REG_RESP_OUT_PTR 0x28 53 #define REG_PREQ_IN_PTR 0x2C 54 #define REG_PREQ_OUT_PTR 0x30 55 #define REG_ATIO_IN_PTR 0x3C 56 #define REG_ATIO_OUT_PTR 0x40 57 58 #define REG_RISC_STATUS 0x44 59 #define REG_HCCR 0x48 60 #define REG_GPIO_DATA 0x4C 61 #define REG_GPIO_ENABLE 0x50 62 #define REG_IOBUS_BASE_ADDR 0x54 63 #define REG_HOST_SEMA 0x58 64 #define REG_MBOX0 0x80 65 66 #define REG_MBOX(n) (REG_MBOX0 + (n << 1)) 67 68 #define MAX_MBOXES 32 69 70 /* 71 * Ctrl Status register definitions 72 */ 73 #define FLASH_ERROR BIT_18 74 #define DMA_ACTIVE_STATUS BIT_17 75 #define DMA_SHUTDOWN_CTRL BIT_16 76 #define FUNCTION_NUMBER BIT_15 77 #define H2RISC_INTR BIT_6 78 #define RISC_RESET BIT_5 79 /* 80 * #define 81XX_FUNCTION_NUMBER BIT_15 | BIT_14 | BIT_13 | BIT_12 81 */ 82 #define PCI_X_BUS_MODE (BIT_8 | BIT_9 | BIT_10 | BIT_11) 83 #define PCI_X_XFER_CTRL (BIT_4 | BIT_5) 84 #define PCI_64_BIT_SLOT BIT_2 85 #define FLASH_WRITE_ENABLE BIT_1 86 #define CHIP_SOFT_RESET BIT_0 87 88 /* 89 * INTR_CTRL register 90 */ 91 #define ENABLE_RISC_INTR BIT_3 92 93 /* 94 * INTR_STATUS register 95 */ 96 #define RISC_PCI_INTR_REQUEST BIT_3 97 98 /* 99 * RISC_STATUS register 100 */ 101 #define FW_INTR_INFO_MASK (BIT_15 | BIT_14 | BIT_13 | BIT_12 | \ 102 BIT_11 | BIT_10 | BIT_9 | BIT_8 | \ 103 BIT_7 | BIT_6 | BIT_5 | BIT_4 | \ 104 BIT_3 | BIT_2 | BIT_1) 105 #define FW_INTR_INFO_SHIFT 18 106 107 #define FW_INTR_INFO(status) (status & (FW_INTR_INFO_MASK << \ 108 FW_INTR_INFO_SHIFT)) 109 #define RISC_HOST_INTR_REQUEST BIT_15 110 #define RISC_PAUSED BIT_8 111 112 #define FW_INTR_STATUS_MASK (BIT_7 | BIT_6 | BIT_5 | BIT_4 | \ 113 BIT_3 | BIT_2 | BIT_1 | BIT_0) 114 115 #define ROM_MBX_CMD_SUCCESSFUL 0x01 116 #define ROM_MBX_CMD_NOT_SUCCESSFUL 0x02 117 #define MBX_CMD_SUCCESSFUL 0x10 118 #define MBX_CMD_NOT_SUCCESSFUL 0x11 119 #define ASYNC_EVENT 0x12 120 #define RESP_Q_UPDATE 0x13 121 #define ATIO_Q_UPDATE 0x1c 122 #define RESP_ATIO_Q_UPDATE 0x1d 123 124 125 /* 126 * Firmware state codes from get firmware state mailbox command 127 */ 128 #define FSTATE_CONFIG_WAIT 0 129 #define FSTATE_WAIT_AL_PA 1 130 #define FSTATE_WAIT_LOGIN 2 131 #define FSTATE_READY 3 132 #define FSTATE_LOSS_SYNC 4 133 #define FSTATE_ERROR 5 134 #define FSTATE_NON_PART 7 135 136 #define FSTATE_MPI_NIC_ERROR 0x10 137 138 139 /* 140 * Mailbox command completion status. 141 */ 142 #define QLT_MBX_CMD_SUCCESS 0x4000 143 144 145 /* 146 * HCCR commands 147 */ 148 #define NOP 0x00 149 #define SET_RISC_RESET 0x01 150 #define CLEAR_RISC_RESET 0x02 151 #define SET_RISC_PAUSE 0x03 152 #define CLEAR_RISC_PAUSE 0x04 153 #define SET_HOST_TO_RISC_INTR 0x05 154 #define CLEAR_HOST_TO_RISC_INTR 0x06 155 #define CLEAR_RISC_TO_PCI_INTR 0x0A 156 157 #define HCCR_CMD_SHIFT 28 158 #define HCCR_CMD(cmd) ((uint32_t)cmd << HCCR_CMD_SHIFT) 159 160 /* 161 * ISP8100/83xx Multi-Queue MBAR definitions 162 */ 163 #define MQBAR_REQ_IN 0x0 164 #define MQBAR_REQ_OUT 0x4 165 #define MQBAR_RESP_IN 0x8 166 #define MQBAR_RESP_OUT 0xc 167 168 #define MQBAR_ATIO_IN 0x10 169 #define MQBAR_ATIO_OUT 0x14 170 171 /* 83xx uses 32 bytes per queue pair */ 172 #define MQBAR_REG_SIZE 0x20 173 #define MQBAR_REG_OFFSET 4096 174 175 #define MQ_MAX_QUEUES 8 176 177 178 /* 179 * Flash/NVRAM definitions 180 */ 181 #define FLASH_DATA_FLAG BIT_31 182 183 #define FLASH_CONF_ADDR 0x7FFD0000 184 185 #define FLASH_DATA_ADDR 0x7FF00000 186 187 #define FLASH_2400_DATA_ADDR 0x7FF00000 188 #define FLASH_2500_DATA_ADDR 0x7FF00000 189 #define FLASH_2700_DATA_ADDR 0x7F800000 190 #define FLASH_8100_DATA_ADDR 0x7F800000 191 #define FLASH_8200_DATA_ADDR 0 192 #define FLASH_8300_DATA_ADDR 0x7F800000 193 194 #define FLASH_DATA_ADDR_81XX 0x7F8D0000 195 /* 0x7F80000 + 0xD0000 */ 196 #define FLASH_DATA_ADDR_83XX 0x7FA70000 197 /* 0x7F80000 + 0x270000 */ 198 199 #define NVRAM_CONF_ADDR 0x7FFF0000 200 #define NVRAM_DATA_ADDR 0x7FFE0000 201 202 #define NVRAM_2400_FUNC0_ADDR 0x80 203 #define NVRAM_2400_FUNC1_ADDR 0x180 204 205 #define NVRAM_2500_FUNC0_ADDR 0x48080 206 #define NVRAM_2500_FUNC1_ADDR 0x48180 207 208 #define NVRAM_2700_FUNC0_ADDR 0x270080 209 #define NVRAM_2700_FUNC1_ADDR 0x270180 210 #define NVRAM_2700_FUNC2_ADDR 0x270280 211 #define NVRAM_2700_FUNC3_ADDR 0x270380 212 213 #define NVRAM_8100_FUNC0_ADDR 0xD0080 214 #define NVRAM_8100_FUNC1_ADDR 0xD0180 215 216 #define NVRAM_8300_FC_FUNC0_ADDR 0x270080 217 #define NVRAM_8300_FC_FUNC1_ADDR 0x270180 218 219 #define NVRAM_8300_FCOE_FUNC0_ADDR 0x274080 220 #define NVRAM_8300_FCOE_FUNC1_ADDR 0x274180 221 222 #define NVRAM_FUNC0_ADDR (NVRAM_DATA_ADDR + 0x80) 223 #define NVRAM_FUNC1_ADDR (NVRAM_DATA_ADDR + 0x180) 224 225 #define QLT25_NVRAM_FUNC0_ADDR (FLASH_DATA_ADDR + 0x48080) 226 #define QLT25_NVRAM_FUNC1_ADDR (FLASH_DATA_ADDR + 0x48180) 227 228 #define QLT27_NVRAM_FUNC0_ADDR (FLASH_2700_DATA_ADDR + 0x270080) 229 #define QLT27_NVRAM_FUNC1_ADDR (FLASH_2700_DATA_ADDR + 0x270180) 230 #define QLT27_NVRAM_FUNC2_ADDR (FLASH_2700_DATA_ADDR + 0x270280) 231 #define QLT27_NVRAM_FUNC3_ADDR (FLASH_2700_DATA_ADDR + 0x270380) 232 233 #define QLT81_NVRAM_FUNC0_ADDR (FLASH_DATA_ADDR_81XX + 0x80) 234 #define QLT81_NVRAM_FUNC1_ADDR (FLASH_DATA_ADDR_81XX + 0x180) 235 236 #define QLT83FC_NVRAM_FUNC0_ADDR (FLASH_DATA_ADDR_83XX + 0x80) 237 #define QLT83FC_NVRAM_FUNC1_ADDR (FLASH_DATA_ADDR_83XX + 0x180) 238 239 #define QLT83FCOE_NVRAM_FUNC0_ADDR (FLASH_DATA_ADDR_83XX + 0x4080) 240 #define QLT83FCOE_NVRAM_FUNC1_ADDR (FLASH_DATA_ADDR_83XX + 0x4180) 241 242 #define VPD_2400_FUNC0_ADDR 0 243 #define VPD_2400_FUNC1_ADDR 0x100 244 245 #define VPD_2500_FUNC0_ADDR 0x48000 246 #define VPD_2500_FUNC1_ADDR 0x48100 247 248 #define VPD_2700_FUNC0_ADDR 0x270000 249 #define VPD_2700_FUNC1_ADDR 0x270100 250 #define VPD_2700_FUNC2_ADDR 0x270200 251 #define VPD_2700_FUNC3_ADDR 0x270300 252 253 #define VPD_8100_FUNC0_ADDR 0xD0000 254 #define VPD_8100_FUNC1_ADDR 0xD0400 255 256 #define VPD_8021_FUNC0_ADDR 0xFA300 257 #define VPD_8021_FUNC1_ADDR 0xFA300 258 259 #define VPD_8300_FC_FUNC0_ADDR 0x270000 260 #define VPD_8300_FC_FUNC1_ADDR 0x270100 261 262 #define VPD_8300_FCOE_FUNC0_ADDR 0x274000 263 #define VPD_8300_FCOE_FUNC1_ADDR 0x274100 264 #define VPD_SIZE 0x80 265 266 #define QLT24_VPD_FUNC0_ADDR (NVRAM_DATA_ADDR + 0x0) 267 #define QLT24_VPD_FUNC1_ADDR (NVRAM_DATA_ADDR + 0x100) 268 269 #define QLT25_VPD_FUNC0_ADDR (FLASH_DATA_ADDR + 0x48000) 270 #define QLT25_VPD_FUNC1_ADDR (FLASH_DATA_ADDR + 0x48100) 271 272 #define QLT27_VPD_FUNC0_ADDR (FLASH_2700_DATA_ADDR + 0x270000) 273 #define QLT27_VPD_FUNC1_ADDR (FLASH_2700_DATA_ADDR + 0x270100) 274 #define QLT27_VPD_FUNC2_ADDR (FLASH_2700_DATA_ADDR + 0x270200) 275 #define QLT27_VPD_FUNC3_ADDR (FLASH_2700_DATA_ADDR + 0x270300) 276 277 #define QLT81_VPD_FUNC0_ADDR (FLASH_8100_DATA_ADDR + 0xD0000) 278 #define QLT81_VPD_FUNC1_ADDR (FLASH_8100_DATA_ADDR + 0xD0400) 279 280 #define QLT83FC_VPD_FUNC0_ADDR (FLASH_8300_DATA_ADDR + 0x270000) 281 #define QLT83FC_VPD_FUNC1_ADDR (FLASH_8300_DATA_ADDR + 0x270100) 282 283 #define QLT83FCOE_VPD_FUNC0_ADDR (FLASH_8300_DATA_ADDR + 0x274000) 284 #define QLT83FCOE_VPD_FUNC1_ADDR (FLASH_8300_DATA_ADDR + 0x274100) 285 286 #define FLASH_2400_FIRMWARE_ADDR 0x20000 287 #define FLASH_2400_FIRMWARE_SIZE 0x10000 288 289 #define FLASH_2500_FIRMWARE_ADDR 0x20000 290 #define FLASH_2500_FIRMWARE_SIZE 0x10000 291 292 #define FLASH_8100_FIRMWARE_ADDR 0xA0000 293 #define FLASH_8100_FIRMWARE_SIZE 0x20000 294 295 #define FLASH_8300_BFE_ADDR 0x200000 /* BIOS/FCode/EFI */ 296 #define FLASH_8300_BFE_SIZE 0x80000 297 298 #define FLASH_8300_FC_FIRMWARE_ADDR 0x240000 299 #define FLASH_8300_FCOE_FIRMWARE_ADDR 0x220000 300 #define FLASH_8300_FIRMWARE_SIZE 0x20000 301 302 #define FLASH_8300_FIRMWARE_IMAGE_ADDR 0x40000 303 #define FLASH_8300_FIRMWARE_IMAGE_SIZE 0x80000 304 305 #define FLASH_8200_BOOTLOADER_ADDR 0x4000 306 #define FLASH_8200_BOOTLOADER_SIZE 0x8000 307 308 #define FLASH_8300_BOOTLOADER_ADDR 0x4000 309 #define FLASH_8300_BOOTLOADER_SIZE 0x8000 310 311 #define FLASH_2400_DESCRIPTOR_TABLE 0 312 #define FLASH_2500_DESCRIPTOR_TABLE 0x50000 313 #define FLASH_8100_DESCRIPTOR_TABLE 0xD8000 314 #define FLASH_8200_DESCRIPTOR_TABLE 0 315 #define FLASH_8300_DESCRIPTOR_TABLE 0xFC000 316 317 #define FLASH_2400_LAYOUT_TABLE 0x11400 318 #define FLASH_2500_LAYOUT_TABLE 0x50400 319 #define FLASH_8100_LAYOUT_TABLE 0xD8400 320 #define FLASH_8200_LAYOUT_TABLE 0xFC400 321 #define FLASH_8300_LAYOUT_TABLE 0xFC400 322 323 #define FLASH_2400_BOOT_CODE_ADDR 0 324 #define FLASH_2500_BOOT_CODE_ADDR 0 325 #define FLASH_2700_BOOT_CODE_ADDR 0x200000 326 #define FLASH_8100_BOOT_CODE_ADDR 0x80000 327 #define FLASH_8300_BOOT_CODE_ADDR 0x200000 328 329 #define VPD_TAG_END 0x78 330 #define VPD_TAG_CHKSUM "RV" 331 #define VPD_TAG_SN "SN" 332 #define VPD_TAG_PN "PN" 333 #define VPD_TAG_PRODID "\x82" 334 #define VPD_TAG_LRT 0x90 335 #define VPD_TAG_LRTC 0x91 336 337 typedef struct qlt_rom_header { 338 uint8_t signature[2]; 339 uint8_t reserved[0x16]; 340 uint8_t dataoffset[2]; 341 uint8_t pad[6]; 342 } qlt_rom_header_t; 343 344 typedef struct qlt_rom_data { 345 uint8_t signature[4]; 346 uint8_t vid[2]; 347 uint8_t did[2]; 348 uint8_t reserved0[2]; 349 uint8_t pcidatalen[2]; 350 uint8_t pcidatarev; 351 uint8_t classcode[3]; 352 uint8_t imagelength[2]; /* In sectors */ 353 uint8_t revisionlevel[2]; 354 uint8_t codetype; 355 uint8_t indicator; 356 uint8_t reserved1[2]; 357 uint8_t pad[8]; 358 } qlt_rom_data_t; 359 360 typedef struct qlt_rom_image { 361 qlt_rom_header_t header; 362 qlt_rom_data_t data; 363 uint32_t cksum; 364 } qlt_rom_image_t; 365 366 #define PCI_HEADER0 0x55 367 #define PCI_HEADER1 0xAA 368 #define PCI_DATASIG "PCIR" 369 #define PCI_SECTOR_SIZE 0x200 370 #define PCI_CODE_X86PC 0 371 #define PCI_CODE_FCODE 1 372 #define PCI_CODE_HPPA 2 373 #define PCI_CODE_EFI 3 374 #define PCI_CODE_FW 0xfe 375 #define PCI_IND_LAST_IMAGE 0x80 376 #define SBUS_CODE_FCODE 0xf1 377 378 /* 379 * Firmware Dump structure definition 380 */ 381 #define QL_2200_FW_DUMP_SIZE 0x68000 /* bytes */ 382 #define QL_2300_FW_DUMP_SIZE 0xE2000 /* bytes */ 383 #define QL_6322_FW_DUMP_SIZE 0xE2000 /* bytes */ 384 #define QL_24XX_FW_DUMP_SIZE 0x0330000 /* bytes */ 385 #define QL_25XX_FW_DUMP_SIZE 0x0330000 /* bytes */ 386 387 #define QL_24XX_VPD_SIZE 0x200 /* bytes */ 388 #define QL_24XX_SFP_SIZE 0x200 /* bytes */ 389 390 #define LNF_NVRAM_DATA BIT_0 391 #define LNF_VPD_DATA BIT_1 392 #define LNF_BFE_DATA BIT_2 393 394 typedef struct qlt_nvram { 395 /* NVRAM header. */ 396 uint8_t id[4]; 397 uint8_t nvram_version[2]; 398 uint8_t reserved_0[2]; 399 400 /* Firmware Initialization Control Block. */ 401 uint8_t version[2]; 402 uint8_t reserved_1[2]; 403 uint8_t max_frame_length[2]; 404 uint8_t execution_throttle[2]; 405 uint8_t exchange_count[2]; 406 uint8_t hard_address[2]; 407 uint8_t port_name[8]; 408 uint8_t node_name[8]; 409 uint8_t login_retry_count[2]; 410 uint8_t link_down_on_nos[2]; 411 uint8_t interrupt_delay_timer[2]; 412 uint8_t login_timeout[2]; 413 414 /* 415 * BIT 0 = Hard Assigned Loop ID 416 * BIT 1 = Enable Fairness 417 * BIT 2 = Enable Full-Duplex 418 * BIT 3 = Reserved 419 * BIT 4 = Target Mode Enable 420 * BIT 5 = Initiator Mode Disable 421 * BIT 6 = Reserved 422 * BIT 7 = Reserved 423 * 424 * BIT 8 = Reserved 425 * BIT 9 = Disable Initial LIP 426 * BIT 10 = Descending Loop ID Search 427 * BIT 11 = Previous Assigned Loop ID 428 * BIT 12 = Reserved 429 * BIT 13 = Full Login after LIP 430 * BIT 14 = Node Name Option 431 * BIT 15-31 = Reserved 432 */ 433 uint8_t firmware_options_1[4]; 434 435 /* 436 * BIT 0 = Operation Mode bit 0 437 * BIT 1 = Operation Mode bit 1 438 * BIT 2 = Operation Mode bit 2 439 * BIT 3 = Operation Mode bit 3 440 * BIT 4 = Connection Options bit 0 441 * BIT 5 = Connection Options bit 1 442 * BIT 6 = Connection Options bit 2 443 * BIT 7 = Enable Non part on LIHA failure 444 * 445 * BIT 8 = Enable Class 2 446 * BIT 9 = Enable ACK0 447 * BIT 10 = Reserved 448 * BIT 11 = Enable FC-SP Security 449 * BIT 12 = FC Tape Enable 450 * BIT 13-31 = Reserved 451 */ 452 uint8_t firmware_options_2[4]; 453 454 /* 455 * BIT 0 = Reserved 456 * BIT 1 = Soft ID only 457 * BIT 2 = Reserved 458 * BIT 3 = Reserved 459 * BIT 4 = FCP RSP Payload bit 0 460 * BIT 5 = FCP RSP Payload bit 1 461 * BIT 6 = Enable Rec Out-of-Order data frame handling 462 * BIT 7 = Disable Automatic PLOGI on Local Loop 463 * 464 * BIT 8 = Reserved 465 * BIT 9 = Enable Out-of-Order FCP_XFER_RDY relative 466 * offset handling 467 * BIT 10 = Reserved 468 * BIT 11 = Reserved 469 * BIT 12 = Reserved 470 * BIT 13 = Data Rate bit 0 471 * BIT 14 = Data Rate bit 1 472 * BIT 15 = Data Rate bit 2 473 * BIT 16 = 75-ohm Termination Select 474 * BIT 17-31 = Reserved 475 */ 476 uint8_t firmware_options_3[4]; 477 478 /* 479 * Serial Link Control (offset 56) 480 * BIT 0 = control enable 481 * BIT 1-15 = Reserved 482 */ 483 uint8_t swing_opt[2]; 484 485 /* 486 * Serial Link Control 1G (offset 58) 487 * BIT 0-7 = Reserved 488 * 489 * BIT 8-10 = output swing 490 * BIT 11-13 = output emphasis 491 * BIT 14-15 = Reserved 492 */ 493 uint8_t swing_1g[2]; 494 495 /* 496 * Serial Link Control 2G (offset 60) 497 * BIT 0-7 = Reserved 498 * 499 * BIT 8-10 = output swing 500 * BIT 11-13 = output emphasis 501 * BIT 14-15 = Reserved 502 */ 503 uint8_t swing_2g[2]; 504 505 /* 506 * Serial Link Control 4G (offset 62) 507 * BIT 0-7 = Reserved 508 * 509 * BIT 8-10 = output swing 510 * BIT 11-13 = output emphasis 511 * BIT 14-15 = Reserved 512 */ 513 uint8_t swing_4g[2]; 514 515 /* Offset 64. */ 516 uint8_t reserved_2[32]; 517 518 /* Offset 96. */ 519 uint8_t reserved_3[32]; 520 521 /* PCIe table entries. */ 522 uint8_t reserved_4[32]; 523 524 /* Offset 160. */ 525 uint8_t reserved_5[32]; 526 527 /* Offset 192. */ 528 uint8_t reserved_6[32]; 529 530 /* Offset 224. */ 531 uint8_t reserved_7[32]; 532 533 /* 534 * BIT 0 = Enable spinup delay 535 * BIT 1 = Disable BIOS 536 * BIT 2 = Enable Memory Map BIOS 537 * BIT 3 = Enable Selectable Boot 538 * BIT 4 = Disable RISC code load 539 * BIT 5 = Disable serdes 540 * BIT 6 = Enable opt boot mode 541 * BIT 7 = Enable int mode BIOS 542 * 543 * BIT 8 = 544 * BIT 9 = 545 * BIT 10 = Enable lip full login 546 * BIT 11 = Enable target reset 547 * BIT 12 = 548 * BIT 13 = Default Node Name Option 549 * BIT 14 = Default valid 550 * BIT 15 = Enable alternate WWN 551 * 552 * BIT 16-31 = 553 */ 554 uint8_t host_p[4]; 555 556 uint8_t alternate_port_name[8]; 557 uint8_t alternate_node_name[8]; 558 559 uint8_t boot_port_name[8]; 560 uint8_t boot_lun_number[2]; 561 uint8_t reserved_8[2]; 562 563 uint8_t alt1_boot_port_name[8]; 564 uint8_t alt1_boot_lun_number[2]; 565 uint8_t reserved_9[2]; 566 567 uint8_t alt2_boot_port_name[8]; 568 uint8_t alt2_boot_lun_number[2]; 569 uint8_t reserved_10[2]; 570 571 uint8_t alt3_boot_port_name[8]; 572 uint8_t alt3_boot_lun_number[2]; 573 uint8_t reserved_11[2]; 574 575 /* 576 * BIT 0 = Selective Login 577 * BIT 1 = Alt-Boot Enable 578 * BIT 2 = Reserved 579 * BIT 3 = Enable Boot Order List 580 * BIT 4 = Reserved 581 * BIT 5 = Enable Selective LUN 582 * BIT 6 = Reserved 583 * BIT 7-31 = 584 */ 585 uint8_t efi_parameters[4]; 586 587 uint8_t reset_delay; 588 uint8_t reserved_12; 589 uint8_t reserved_13[2]; 590 591 uint8_t boot_id_number[2]; 592 uint8_t reserved_14[2]; 593 594 uint8_t max_luns_per_target[2]; 595 uint8_t reserved_15[2]; 596 597 uint8_t port_down_retry_count[2]; 598 uint8_t link_down_timeout[2]; 599 600 /* 601 * FCode parameters word (offset 344) 602 * 603 * BIT 0 = Enable BIOS pathname 604 * BIT 1 = fcode qlc 605 * BIT 2 = fcode host 606 * BIT 3-7 = 607 */ 608 uint8_t fcode_p0; 609 uint8_t reserved_16[7]; 610 611 /* Offset 352. */ 612 uint8_t prev_drv_ver_major; 613 uint8_t prev_drv_ver_submajob; 614 uint8_t prev_drv_ver_minor; 615 uint8_t prev_drv_ver_subminor; 616 617 uint8_t prev_bios_ver_major[2]; 618 uint8_t prev_bios_ver_minor[2]; 619 620 uint8_t prev_efi_ver_major[2]; 621 uint8_t prev_efi_ver_minor[2]; 622 623 uint8_t prev_fw_ver_major[2]; 624 uint8_t prev_fw_ver_minor; 625 uint8_t prev_fw_ver_subminor; 626 627 uint8_t reserved_17[16]; 628 629 /* Offset 384. */ 630 uint8_t def_port_name[8]; 631 uint8_t def_node_name[8]; 632 633 uint8_t reserved_18[16]; 634 635 /* Offset 416. */ 636 uint8_t reserved_19[32]; 637 638 /* Offset 448. */ 639 uint8_t reserved_20[28]; 640 641 /* Offset 476. */ 642 uint8_t fw_table_offset[2]; 643 uint8_t fw_table_sig[2]; 644 645 /* Offset 480. */ 646 uint8_t model_name[8]; 647 648 /* Offset 488. */ 649 uint8_t power_table[16]; 650 651 uint8_t subsystem_vendor_id[2]; 652 uint8_t subsystem_device_id[2]; 653 654 uint8_t checksum[4]; 655 } qlt_nvram_t; 656 657 /* ISP81xx Extended Initialisation Control Block */ 658 typedef struct qlt_ext_icb_81xx { 659 660 uint8_t version[2]; 661 uint8_t fcf_vlan_match; 662 uint8_t reserved_6[3]; 663 uint8_t fcf_vlan_id[2]; 664 uint8_t fcf_fabric_name[8]; 665 uint8_t reserved_7[14]; 666 uint8_t spma_proposed_mac_address[6]; 667 uint8_t reserved_8[28]; 668 669 } qlt_ext_icb_81xx_t; 670 671 typedef struct qlt_nvram_81xx { 672 /* NVRAM header. */ 673 uint8_t id[4]; 674 uint8_t nvram_version[2]; 675 uint8_t reserved_0[2]; 676 677 /* Firmware Initialization Control Block. */ 678 uint8_t version[2]; 679 uint8_t reserved_1[2]; 680 uint8_t max_frame_length[2]; 681 uint8_t execution_throttle[2]; 682 uint8_t exchange_count[2]; 683 uint8_t reserved_2[2]; 684 uint8_t port_name[8]; 685 uint8_t node_name[8]; 686 uint8_t login_retry_count[2]; 687 uint8_t reserved_3[2]; 688 uint8_t interrupt_delay_timer[2]; 689 uint8_t login_timeout[2]; 690 691 /* 692 * BIT 0 = Hard Assigned Loop ID 693 * BIT 1 = Enable Fairness 694 * BIT 2 = Enable Full-Duplex 695 * BIT 3 = Reserved 696 * BIT 4 = Target Mode Enable 697 * BIT 5 = Initiator Mode Disable 698 * BIT 6 = Reserved 699 * BIT 7 = Reserved 700 * 701 * BIT 8 = Reserved 702 * BIT 9 = Reserved 703 * BIT 10 = Reserved 704 * BIT 11 = Reserved 705 * BIT 12 = Reserved 706 * BIT 13 = Reserved 707 * BIT 14 = Node Name Option 708 * BIT 15-31 = Reserved 709 */ 710 uint8_t firmware_options_1[4]; 711 712 /* 713 * BIT 0 = Operation Mode bit 0 714 * BIT 1 = Operation Mode bit 1 715 * BIT 2 = Operation Mode bit 2 716 * BIT 3 = Operation Mode bit 3 717 * BIT 4 = Reserved 718 * BIT 5 = Reserved 719 * BIT 6 = Reserved 720 * BIT 7 = Reserved 721 * 722 * BIT 8 = Enable Class 2 723 * BIT 9 = Enable ACK0 724 * BIT 10 = Reserved 725 * BIT 11 = Enable FC-SP Security 726 * BIT 12 = FC Tape Enable 727 * BIT 13 = Reserved 728 * BIT 14 = Target PRLI Control 729 * BIT 15-31 = Reserved 730 */ 731 uint8_t firmware_options_2[4]; 732 733 /* 734 * BIT 0 = Reserved 735 * BIT 1 = Soft ID only 736 * BIT 2 = Reserved 737 * BIT 3 = Reserved 738 * BIT 4 = FCP RSP Payload bit 0 739 * BIT 5 = FCP RSP Payload bit 1 740 * BIT 6 = Enable Rec Out-of-Order data frame handling 741 * BIT 7 = Reserved 742 * 743 * BIT 8 = Reserved 744 * BIT 9 = Enable Out-of-Order FCP_XFER_RDY relative 745 * offset handling 746 * BIT 10 = Reserved 747 * BIT 11 = Reserved 748 * BIT 12 = Reserved 749 * BIT 13 = Reserved 750 * BIT 14 = Reserved 751 * BIT 15 = Reserved 752 * BIT 16 = Reserved 753 * BIT 17 = Enable Multiple FCFs 754 * BIT 18-20 = MAC Addressing Mode 755 * BIT 21-25 = Ethernet Data Rate 756 * BIT 26 = Enable Ethernet Header Receive ATIO_Q 757 * BIT 27 = Enable Ethernet Header Receive RSP_Q 758 * BIT 28-29 = SPMA Selection 759 * BIT 30-31 = Reserved 760 */ 761 uint8_t firmware_options_3[4]; 762 763 /* Offset 56 (38h). */ 764 uint8_t reserved_4[8]; 765 766 /* Offset 64 (40h). */ 767 uint8_t enode_mac[6]; 768 769 /* Offset 70 (46h). */ 770 uint8_t reserved_5[26]; 771 772 /* Offset 96 (60h). */ 773 uint8_t oem_specific; 774 uint8_t reserved_6[15]; 775 776 /* Offset 112 (70h). */ 777 uint8_t reserved_7[16]; 778 779 /* Offset 128 (80h). */ 780 qlt_ext_icb_81xx_t ext_blk; 781 782 /* Offset 192. */ 783 uint8_t reserved_8[32]; 784 785 /* Offset 224. */ 786 uint8_t reserved_9[32]; 787 788 uint8_t host_p[4]; 789 790 uint8_t alternate_port_name[8]; 791 uint8_t alternate_name_name[8]; 792 793 uint8_t boot_port_name[8]; 794 uint8_t boot_lun_number[2]; 795 uint8_t reserved_10[2]; 796 797 uint8_t alt1_boot_port_name[8]; 798 uint8_t alt1_boot_lun_number[2]; 799 uint8_t reserved_11[2]; 800 801 uint8_t alt2_boot_port_name[8]; 802 uint8_t alt2_boot_lun_number[2]; 803 uint8_t reserved_12[2]; 804 805 uint8_t alt3_boot_port_name[8]; 806 uint8_t alt3_boot_lun_number[2]; 807 uint8_t reserved_13[2]; 808 809 /* 810 * BIT 0 = Selective Login 811 * BIT 1 = Alt-Boot Enable 812 * BIT 2 = Reserved 813 * BIT 3 = Enable Boot Order List 814 * BIT 4 = Reserved 815 * BIT 5 = Enable Selective LUN 816 * BIT 6 = Reserved 817 * BIT 7-31 = 818 */ 819 uint8_t efi_parameters[4]; 820 821 uint8_t reset_delay; 822 uint8_t reserved_14; 823 uint8_t reserved_15[2]; 824 825 uint8_t boot_id_number[2]; 826 uint8_t reserved_16[2]; 827 828 uint8_t max_luns_per_target[2]; 829 uint8_t reserved_17[2]; 830 831 uint8_t port_down_retry_count[2]; 832 uint8_t link_down_timeout[2]; 833 834 /* 835 * FCode parameters word (offset 344) 836 * 837 * BIT 0 = Enable BIOS pathname 838 * BIT 1 = fcode qlc 839 * BIT 2 = fcode host 840 * BIT 3-7 = 841 */ 842 uint8_t fcode_parameter[2]; 843 uint8_t reserved_18[6]; 844 845 /* Offset 352. */ 846 uint8_t reserved_19[4]; 847 uint8_t reserved_20[10]; 848 uint8_t reserved_21[2]; 849 uint8_t reserved_22[16]; 850 851 /* Offset 384. */ 852 uint8_t reserved_23[16]; 853 uint8_t reserved_24[16]; 854 855 /* Offset 416. */ 856 uint8_t reserved_25[64]; 857 858 /* Offset 480. */ 859 uint8_t model_name[16]; 860 861 /* Offset 496. */ 862 uint8_t feature_mask_l[2]; 863 uint8_t feature_mask_h[2]; 864 uint8_t reserved_26[4]; 865 866 uint8_t subsystem_vendor_id[2]; 867 uint8_t subsystem_device_id[2]; 868 869 uint8_t checksum[4]; 870 871 } qlt_nvram_81xx_t; 872 873 /* 874 * firmware dump Entry Types 875 */ 876 #define DT_NOP 0 877 #define DT_THDR 99 878 #define DT_TEND 255 879 #define DT_RIOB1 256 880 #define DT_WIOB1 257 881 #define DT_RIOB2 258 882 #define DT_WIOB2 259 883 #define DT_RPCI 260 884 #define DT_WPCI 261 885 #define DT_RRAM 262 886 #define DT_GQUE 263 887 #define DT_GFCE 264 888 #define DT_PRISC 265 889 #define DT_RRISC 266 890 #define DT_DINT 267 891 #define DT_GHBD 268 892 #define DT_SCRA 269 893 #define DT_RRREG 270 894 #define DT_WRREG 271 895 #define DT_RRRAM 272 896 #define DT_RPCIC 273 897 #define DT_GQUES 274 898 #define DT_WDMP 275 899 900 /* 901 * firmware dump Template Header (Entry Type 99) 902 */ 903 typedef struct qlt_dt_hdr { 904 uint32_t type; 905 uint32_t first_entry_offset; 906 uint32_t size_of_template; 907 uint32_t rsv; 908 uint32_t num_of_entries; 909 uint32_t version; 910 uint32_t driver_timestamp; 911 uint32_t checksum; 912 uint32_t rsv_1; 913 uint32_t driver_info[3]; 914 uint32_t saved_state_area[16]; 915 uint32_t rsv_2[8]; 916 uint32_t ver_attr[5]; 917 } qlt_dt_hdr_t; 918 919 /* 920 * firmware dump Common Entry Header 921 */ 922 typedef struct qlt_dt_entry_hdr { 923 uint32_t type; 924 uint32_t size; 925 uint32_t rsv; 926 #ifdef _BIG_ENDIAN 927 uint8_t driver_flags; 928 uint8_t rsv_2; 929 uint8_t rsv_1; 930 uint8_t capture_flags; 931 #else 932 uint8_t capture_flags; 933 uint8_t rsv_1; 934 uint8_t rsv_2; 935 uint8_t driver_flags; 936 #endif 937 } qlt_dt_entry_hdr_t; 938 939 /* 940 * Capture Flags 941 */ 942 #define PF_ONLY_FLAG BIT_0 /* Physical Function Only */ 943 #define PF_VF_FLAG BIT_1 /* Physical and Virtual Functions */ 944 945 /* 946 * Driver Flags 947 */ 948 #define SKIPPED_FLAG BIT_7 /* driver skipped this entry */ 949 950 /* 951 * firmware dump Entry Including Header 952 */ 953 typedef struct qlt_dt_entry { 954 qlt_dt_entry_hdr_t h; 955 uint32_t data[1]; 956 } qlt_dt_entry_t; 957 958 /* 959 * firmware dump Template image 960 */ 961 typedef struct qlt_dmp_template { 962 uint32_t rsv[2]; 963 uint32_t len; 964 uint32_t major_ver; 965 uint32_t minor_ver; 966 uint32_t subminor_ver; 967 uint32_t attribute; 968 qlt_dt_hdr_t hdr; 969 qlt_dt_entry_t entries[1]; 970 } qlt_dmp_template_t; 971 972 typedef struct qlt_dt_riob1 { 973 qlt_dt_entry_hdr_t h; 974 uint32_t addr; 975 #ifdef _BIG_ENDIAN 976 uint8_t pci_offset; 977 uint8_t reg_count_h; 978 uint8_t reg_count_l; 979 uint8_t reg_size; 980 #else 981 uint8_t reg_size; 982 uint8_t reg_count_l; 983 uint8_t reg_count_h; 984 uint8_t pci_offset; 985 #endif 986 } qlt_dt_riob1_t; 987 988 typedef struct qlt_dt_wiob1 { 989 qlt_dt_entry_hdr_t h; 990 uint32_t addr; 991 uint32_t data; 992 #ifdef _BIG_ENDIAN 993 uint8_t rsv[3]; 994 uint8_t pci_offset; 995 #else 996 uint8_t pci_offset; 997 uint8_t rsv[3]; 998 #endif 999 } qlt_dt_wiob1_t; 1000 1001 typedef struct qlt_dt_riob2 { 1002 qlt_dt_entry_hdr_t h; 1003 uint32_t addr; 1004 #ifdef _BIG_ENDIAN 1005 uint8_t pci_offset; 1006 uint8_t reg_count_h; 1007 uint8_t reg_count_l; 1008 uint8_t reg_size; 1009 uint8_t rsv[3]; 1010 uint8_t bank_sel_offset; 1011 #else 1012 uint8_t reg_size; 1013 uint8_t reg_count_l; 1014 uint8_t reg_count_h; 1015 uint8_t pci_offset; 1016 uint8_t bank_sel_offset; 1017 uint8_t rsv[3]; 1018 #endif 1019 uint32_t reg_bank; 1020 } qlt_dt_riob2_t; 1021 1022 typedef struct qlt_dt_wiob2 { 1023 qlt_dt_entry_hdr_t h; 1024 uint32_t addr; 1025 #ifdef _BIG_ENDIAN 1026 uint8_t rsv[2]; 1027 uint8_t data_h; 1028 uint8_t data_l; 1029 uint8_t bank_sel_offset; 1030 uint8_t pci_offset; 1031 uint8_t rsv1[2]; 1032 #else 1033 uint8_t data_l; 1034 uint8_t data_h; 1035 uint8_t rsv[2]; 1036 uint8_t rsv1[2]; 1037 uint8_t pci_offset; 1038 uint8_t bank_sel_offset; 1039 #endif 1040 uint32_t reg_bank; 1041 } qlt_dt_wiob2_t; 1042 1043 typedef struct qlt_dt_rpci { 1044 qlt_dt_entry_hdr_t h; 1045 uint32_t addr; 1046 } qlt_dt_rpci_t; 1047 1048 typedef struct qlt_dt_wpci { 1049 qlt_dt_entry_hdr_t h; 1050 uint32_t addr; 1051 uint32_t data; 1052 } qlt_dt_wpci_t, qlt_dt_wrreg_t; 1053 1054 typedef struct qlt_dt_rram { 1055 qlt_dt_entry_hdr_t h; 1056 #ifdef _BIG_ENDIAN 1057 uint8_t rsv[3]; 1058 uint8_t ram_area; 1059 #else 1060 uint8_t ram_area; 1061 uint8_t rsv[3]; 1062 #endif 1063 uint32_t start_addr; 1064 uint32_t end_addr; 1065 } qlt_dt_rram_t; 1066 1067 typedef struct qlt_dt_gque { 1068 qlt_dt_entry_hdr_t h; 1069 uint32_t num_queues; 1070 #ifdef _BIG_ENDIAN 1071 uint8_t rsv[3]; 1072 uint8_t queue_type; 1073 #else 1074 uint8_t queue_type; 1075 uint8_t rsv[3]; 1076 #endif 1077 } qlt_dt_gque_t, qlt_dt_gques_t; 1078 1079 typedef struct qlt_dt_gfce { 1080 qlt_dt_entry_hdr_t h; 1081 uint32_t fce_trace_size; 1082 uint32_t write_pointer[2]; 1083 uint32_t base_pointer[2]; 1084 uint32_t fce_enable_mb0; 1085 uint32_t fce_enable_mb2; 1086 uint32_t fce_enable_mb3; 1087 uint32_t fce_enable_mb4; 1088 uint32_t fce_enable_mb5; 1089 uint32_t fce_enable_mb6; 1090 } qlt_dt_gfce_t; 1091 1092 typedef struct qlt_dt_prisc { 1093 qlt_dt_entry_hdr_t h; 1094 } qlt_dt_prisc_t, qlt_dt_rrisc_t; 1095 1096 typedef struct qlt_dt_dint { 1097 qlt_dt_entry_hdr_t h; 1098 #ifdef _BIG_ENDIAN 1099 uint8_t rsv[3]; 1100 uint8_t pci_offset; 1101 #else 1102 uint8_t pci_offset; 1103 uint8_t rsv[3]; 1104 #endif 1105 uint32_t data; 1106 } qlt_dt_dint_t; 1107 1108 typedef struct qlt_dt_ghbd { 1109 qlt_dt_entry_hdr_t h; 1110 #ifdef _BIG_ENDIAN 1111 uint8_t rsv[3]; 1112 uint8_t host_buf_type; 1113 #else 1114 uint8_t host_buf_type; 1115 uint8_t rsv[3]; 1116 #endif 1117 uint32_t buf_size; 1118 uint32_t start_addr; 1119 } qlt_dt_ghbd_t; 1120 1121 typedef struct qlt_dt_scra { 1122 qlt_dt_entry_hdr_t h; 1123 uint32_t scratch_size; 1124 } qlt_dt_scra_t; 1125 1126 typedef struct qlt_dt_rrreg { 1127 qlt_dt_entry_hdr_t h; 1128 uint32_t addr; 1129 uint32_t count; 1130 } qlt_dt_rrreg_t, qlt_dt_rrram_t, qlt_dt_rpcic_t; 1131 1132 typedef struct qlt_dt_wdmp { 1133 qlt_dt_entry_hdr_t h; 1134 uint32_t length; 1135 uint32_t data[1]; 1136 } qlt_dt_wdmp_t; 1137 1138 #ifdef __cplusplus 1139 } 1140 #endif 1141 1142 #endif /* _QLT_REGS_H */ 1143