1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * Copyright 2024 Racktop Systems, Inc. 14 */ 15 16 #ifndef _MFI_PD_H 17 #define _MFI_PD_H 18 19 #include <sys/scsi/adapters/mfi/mfi.h> 20 21 #ifdef __cplusplus 22 extern "C" { 23 #endif 24 25 #define MFI_PD_STATE_UNCONFIGURED_GOOD 0x00 26 #define MFI_PD_STATE_UNCONFIGURED_BAD 0x01 27 #define MFI_PD_STATE_HOT_SPARE 0x02 28 #define MFI_PD_STATE_OFFLINE 0x10 29 #define MFI_PD_STATE_FAILED 0x11 30 #define MFI_PD_STATE_REBUILD 0x14 31 #define MFI_PD_STATE_ONLINE 0x18 32 #define MFI_PD_STATE_COPYBACK 0x20 33 #define MFI_PD_STATE_SYSTEM 0x40 34 35 #define MFI_PD_CACHE_UNCHANGED 0 36 #define MFI_PD_CACHE_ENABLE 1 37 #define MFI_PD_CACHE_DISABLE 2 38 39 #pragma pack(1) 40 41 /* 42 * PD reference 43 */ 44 struct mfi_pd_ref { 45 uint16_t pr_dev_id; 46 uint16_t pr_seqnum; 47 }; 48 CTASSERT(sizeof (mfi_pd_ref_t) == 4); 49 50 /* 51 * PD info 52 */ 53 struct mfi_pd_info { 54 mfi_pd_ref_t pd_ref; 55 uint8_t pd_inq[96]; 56 uint8_t pd_vpd83[64]; 57 uint8_t pd_notsup; 58 uint8_t pd_scsi_dev_type; 59 60 union { 61 uint8_t pd_conn_port_bitmap; 62 uint8_t pd_conn_port_num; 63 }; 64 65 uint8_t pd_dev_speed; 66 uint32_t pd_media_err_cnt; 67 uint32_t pd_other_err_cnt; 68 uint32_t pd_pred_fail_cnt; 69 uint32_t pd_last_pred_fail_evt_seqnum; 70 71 uint16_t pd_fw_state; 72 uint8_t pd_disabled_for_removal; 73 uint8_t pd_link_speed; 74 75 struct { 76 uint32_t pd_forced_pd_guid:1; 77 uint32_t pd_in_vd:1; 78 uint32_t pd_is_global_spare:1; 79 uint32_t pd_is_spare:1; 80 uint32_t pd_is_foreign:1; 81 uint32_t pd_rsvd:7; 82 uint32_t pd_intf:4; 83 uint32_t pd_rsvd2:16; 84 } pd_ddf_type; 85 86 struct { 87 uint8_t pi_count; 88 uint8_t pi_path_broken:4; 89 uint8_t pi_rsvd:3; 90 uint8_t pi_wide_port_cap:1; 91 uint8_t pi_conn_idx[2]; 92 uint8_t pi_rsvd2[4]; 93 uint64_t pi_sas_addr[2]; 94 uint8_t pi_rsvd3[16]; 95 } pd_pathinfo; 96 97 uint64_t pd_raw_size; 98 uint64_t pd_non_coerced_size; 99 uint64_t pd_coerced_size; 100 101 uint16_t pd_encl_dev_id; 102 uint8_t pd_encl_idx; 103 104 union { 105 uint8_t pd_slot_num; 106 uint8_t pd_encl_conn_idx; 107 }; 108 109 struct { 110 uint32_t pp_active_rbld:1; 111 uint32_t pp_active_patrol:1; 112 uint32_t pp_active_clear:1; 113 uint32_t pp_active_copyback:1; 114 uint32_t pp_active_erase:1; 115 uint32_t pp_active_locate:1; 116 uint32_t pp_active_rsvd:26; 117 118 mfi_progress_t pp_rbld; 119 mfi_progress_t pp_patrol; 120 mfi_progress_t pp_clear; 121 122 uint32_t pp_pause_rbld:1; 123 uint32_t pp_pause_patrol:1; 124 uint32_t pp_pause_clear:1; 125 uint32_t pp_pause_copyback:1; 126 uint32_t pp_pause_erase:1; 127 uint32_t pp_pause_rsvd:27; 128 129 uint32_t pp_rsvd[3]; 130 } pd_progress; 131 132 uint8_t pd_bad_block_table_full; 133 uint8_t pd_unusable_in_current_config; 134 uint8_t pd_vpd83ext[64]; 135 uint8_t pd_powerstate; 136 uint8_t pd_encl_pos; 137 uint32_t pd_allowed_ops; 138 uint16_t pd_copyback_partner_id; 139 uint16_t pd_encl_partner_dev_id; 140 141 struct { 142 uint16_t ps_fde_capable:1; 143 uint16_t ps_fde_enabled:1; 144 uint16_t ps_secured:1; 145 uint16_t ps_locked:1; 146 uint16_t ps_foreign:1; 147 uint16_t ps_needs_EKM:1; 148 uint16_t ps_rsvd:10; 149 } pd_security; 150 151 uint8_t pd_mediatype; 152 uint8_t pd_not_certified; 153 uint8_t pd_bridge_vendor[8]; 154 uint8_t pd_bridge_product_id[16]; 155 uint8_t pd_bridge_product_rev[4]; 156 uint8_t pd_sat_bridge_exists; 157 158 uint8_t pd_interface_type; 159 uint8_t pd_temperature; 160 uint8_t pd_emulated_blocksize; 161 uint16_t pd_userdata_blocksize; 162 uint16_t pd_rsvd; 163 164 struct { 165 uint32_t pp_pi_type:3; 166 uint32_t pp_pi_formatted:1; 167 uint32_t pp_pi_eligible:1; 168 uint32_t pp_ncq:1; 169 uint32_t pp_wce:1; 170 uint32_t pp_comm_spare:1; 171 uint32_t pp_emerg_spare:1; 172 uint32_t pp_ineligible_for_sscd:1; 173 uint32_t pp_ineligible_for_ld:1; 174 uint32_t pp_use_ss_erase_type:1; 175 uint32_t pp_wce_unchanged:1; 176 uint32_t pp_support_scsi_unmap:1; 177 uint32_t pp_rsvd:18; 178 } pd_prop; 179 180 uint64_t pd_shield_diag_compl_time; 181 uint8_t pd_shield_counter; 182 183 uint8_t pd_link_speed_other; 184 uint8_t pd_rsvd2[2]; 185 186 struct { 187 uint32_t bbm_err_count_supported:1; 188 uint32_t bbm_err_count:31; 189 } pd_bbm_err; 190 191 uint8_t pd_rsvd3[512 - 428]; 192 }; 193 /* 194 * For some reason, smatch gets mfi_pd_info_t wrong. Apparently it sees 195 * 4 bytes of padding following pd_prop despite packing of the struct. 196 */ 197 #ifndef __CHECKER__ 198 CTASSERT(sizeof (mfi_pd_info_t) == 512); 199 #endif 200 201 /* 202 * PD config map 203 */ 204 struct mfi_pd_cfg { 205 uint16_t pd_seqnum; 206 uint16_t pd_devhdl; 207 struct { 208 uint8_t pd_tm_capable:1; 209 uint8_t pd_rsvd:7; 210 }; 211 uint8_t pd_rsvd2; 212 uint16_t pd_tgtid; 213 }; 214 CTASSERT(sizeof (mfi_pd_cfg_t) == 8); 215 216 struct mfi_pd_map { 217 uint32_t pm_size; 218 uint32_t pm_count; 219 mfi_pd_cfg_t pm_pdcfg[0]; 220 }; 221 222 /* 223 * PD address list 224 */ 225 struct mfi_pd_addr { 226 uint16_t pa_dev_id; 227 uint16_t pa_enc_id; 228 229 union { 230 struct { 231 uint8_t pa_enc_idx; 232 uint8_t pa_slot_num; 233 }; 234 struct { 235 uint8_t pa_enc_pos; 236 uint8_t pa_enc_conn_idx; 237 }; 238 }; 239 uint8_t pa_scsi_dev_type; 240 union { 241 uint8_t pa_conn_port_bitmap; 242 uint8_t pa_conn_port_numbers; 243 }; 244 uint64_t pa_sas_addr[2]; 245 }; 246 CTASSERT(sizeof (mfi_pd_addr_t) == 24); 247 248 struct mfi_pd_list { 249 uint32_t pl_size; 250 uint32_t pl_count; 251 mfi_pd_addr_t pl_addr[0]; 252 }; 253 254 #pragma pack(0) 255 256 #ifdef __cplusplus 257 } 258 #endif 259 260 #endif /* _MFI_PD_H */ 261