1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2011 NetApp, Inc.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28 /*
29 * Copyright 2018 Joyent, Inc.
30 * Copyright 2025 Oxide Computer Company
31 */
32
33 #ifndef _PCI_EMUL_H_
34 #define _PCI_EMUL_H_
35
36 #include <sys/types.h>
37 #include <sys/queue.h>
38 #include <sys/kernel.h>
39 #include <sys/nv.h>
40 #include <sys/pciio.h>
41 #include <sys/_pthreadtypes.h>
42
43 #include <dev/pci/pcireg.h>
44
45 #include <assert.h>
46
47 #define PCI_BARMAX PCIR_MAX_BAR_0 /* BAR registers in a Type 0 header */
48 #define PCI_BARMAX_WITH_ROM (PCI_BARMAX + 1)
49 #define PCI_ROM_IDX (PCI_BARMAX + 1)
50
51 struct vmctx;
52 struct pci_devinst;
53 struct memory_region;
54
55 struct pci_devemu {
56 const char *pe_emu; /* Name of device emulation */
57
58 /* instance creation */
59 int (*pe_init)(struct pci_devinst *, nvlist_t *);
60 int (*pe_legacy_config)(nvlist_t *, const char *);
61 const char *pe_alias;
62
63 /* ACPI DSDT enumeration */
64 void (*pe_write_dsdt)(struct pci_devinst *);
65
66 /* config space read/write callbacks */
67 int (*pe_cfgwrite)(struct pci_devinst *pi, int offset,
68 int bytes, uint32_t val);
69 int (*pe_cfgread)(struct pci_devinst *pi, int offset,
70 int bytes, uint32_t *retval);
71
72 /* BAR read/write callbacks */
73 void (*pe_barwrite)(struct pci_devinst *pi, int baridx,
74 uint64_t offset, int size, uint64_t value);
75 uint64_t (*pe_barread)(struct pci_devinst *pi, int baridx,
76 uint64_t offset, int size);
77
78 void (*pe_baraddr)(struct pci_devinst *pi,
79 int baridx, int enabled, uint64_t address);
80 #ifndef __FreeBSD__
81 void (*pe_lintrupdate)(struct pci_devinst *pi);
82 #endif /* __FreeBSD__ */
83 };
84 #define PCI_EMUL_SET(x) DATA_SET(pci_devemu_set, x)
85
86 /*
87 * These values are returned by the config space read/write callbacks
88 * (pe_cfgwrite and pe_cfgread in the above structure).
89 *
90 * A return value of PE_CFGRW_DEFAULT will cause the PCI emulation framework to
91 * continue on and access the configuration space as if the callback did not
92 * exist, whereas PE_CFGRW_DROP will not.
93 */
94 #define PE_CFGRW_DROP (0)
95 #define PE_CFGRW_DEFAULT (1)
96
97 enum pcibar_type {
98 PCIBAR_NONE,
99 PCIBAR_IO,
100 PCIBAR_MEM32,
101 PCIBAR_MEM64,
102 PCIBAR_MEMHI64,
103 PCIBAR_ROM,
104 };
105
106 struct pcibar {
107 enum pcibar_type type; /* io or memory */
108 uint64_t size;
109 uint64_t addr;
110 uint8_t lobits;
111 };
112
113 #define PI_NAMESZ 40
114
115 struct msix_table_entry {
116 uint64_t addr;
117 uint32_t msg_data;
118 uint32_t vector_control;
119 } __packed;
120
121 /*
122 * In case the structure is modified to hold extra information, use a define
123 * for the size that should be emulated.
124 */
125 #define MSIX_TABLE_ENTRY_SIZE 16
126 #define MAX_MSIX_TABLE_ENTRIES 2048
127 #define PBA_SIZE(msgnum) (roundup2((msgnum), 64) / 8)
128
129 enum lintr_stat {
130 IDLE,
131 ASSERTED,
132 PENDING
133 };
134
135 struct pci_devinst {
136 struct pci_devemu *pi_d;
137 struct vmctx *pi_vmctx;
138 uint8_t pi_bus, pi_slot, pi_func;
139 char pi_name[PI_NAMESZ];
140 int pi_bar_getsize;
141 int pi_prevcap;
142 int pi_capend;
143
144 struct {
145 int8_t pin;
146 enum lintr_stat state;
147 int pirq_pin;
148 int ioapic_irq;
149 pthread_mutex_t lock;
150 } pi_lintr;
151
152 struct {
153 int enabled;
154 uint64_t addr;
155 uint64_t msg_data;
156 int maxmsgnum;
157 } pi_msi;
158
159 struct {
160 int enabled;
161 int table_bar;
162 int pba_bar;
163 uint32_t table_offset;
164 int table_count;
165 uint32_t pba_offset;
166 int pba_size;
167 int function_mask;
168 struct msix_table_entry *table; /* allocated at runtime */
169 void *pba_page;
170 int pba_page_offset;
171 uint8_t *mapped_addr;
172 size_t mapped_size;
173 } pi_msix;
174
175 void *pi_arg; /* devemu-private data */
176
177 u_char pi_cfgdata[PCI_REGMAX + 1];
178 /* ROM is handled like a BAR */
179 struct pcibar pi_bar[PCI_BARMAX_WITH_ROM + 1];
180 uint64_t pi_romoffset;
181 };
182
183 struct msicap {
184 uint8_t capid;
185 uint8_t nextptr;
186 uint16_t msgctrl;
187 uint32_t addrlo;
188 uint32_t addrhi;
189 uint16_t msgdata;
190 } __packed;
191 static_assert(sizeof(struct msicap) == 14, "compile-time assertion failed");
192
193 struct msixcap {
194 uint8_t capid;
195 uint8_t nextptr;
196 uint16_t msgctrl;
197 uint32_t table_info; /* bar index and offset within it */
198 uint32_t pba_info; /* bar index and offset within it */
199 } __packed;
200 static_assert(sizeof(struct msixcap) == 12, "compile-time assertion failed");
201
202 struct pciecap {
203 uint8_t capid;
204 uint8_t nextptr;
205 uint16_t pcie_capabilities;
206
207 uint32_t dev_capabilities; /* all devices */
208 uint16_t dev_control;
209 uint16_t dev_status;
210
211 uint32_t link_capabilities; /* devices with links */
212 uint16_t link_control;
213 uint16_t link_status;
214
215 uint32_t slot_capabilities; /* ports with slots */
216 uint16_t slot_control;
217 uint16_t slot_status;
218
219 uint16_t root_control; /* root ports */
220 uint16_t root_capabilities;
221 uint32_t root_status;
222
223 uint32_t dev_capabilities2; /* all devices */
224 uint16_t dev_control2;
225 uint16_t dev_status2;
226
227 uint32_t link_capabilities2; /* devices with links */
228 uint16_t link_control2;
229 uint16_t link_status2;
230
231 uint32_t slot_capabilities2; /* ports with slots */
232 uint16_t slot_control2;
233 uint16_t slot_status2;
234 } __packed;
235 static_assert(sizeof(struct pciecap) == 60, "compile-time assertion failed");
236
237 typedef void (*pci_lintr_cb)(int b, int s, int pin, int pirq_pin,
238 int ioapic_irq, void *arg);
239
240 int init_pci(struct vmctx *ctx);
241 void pci_callback(void);
242 uint32_t pci_config_read_reg(const struct pcisel *host_sel, nvlist_t *nvl,
243 uint32_t reg, uint8_t size, uint32_t def);
244 int pci_emul_alloc_bar(struct pci_devinst *pdi, int idx,
245 enum pcibar_type type, uint64_t size);
246 int pci_emul_alloc_rom(struct pci_devinst *const pdi, const uint64_t size,
247 void **const addr);
248 int pci_emul_add_boot_device(struct pci_devinst *const pi,
249 const int bootindex);
250 int pci_emul_add_capability(struct pci_devinst *pi, u_char *capdata,
251 int caplen, int *capoffp);
252 int pci_emul_add_msicap(struct pci_devinst *pi, int msgnum);
253 int pci_emul_add_pciecap(struct pci_devinst *pi, int pcie_device_type);
254 void pci_emul_capwrite(struct pci_devinst *pi, int offset, int bytes,
255 uint32_t val, uint8_t capoff, int capid);
256 void pci_emul_cmd_changed(struct pci_devinst *pi, uint16_t old);
257 void pci_generate_msi(struct pci_devinst *pi, int msgnum);
258 void pci_generate_msix(struct pci_devinst *pi, int msgnum);
259 void pci_lintr_assert(struct pci_devinst *pi);
260 void pci_lintr_deassert(struct pci_devinst *pi);
261 void pci_lintr_request(struct pci_devinst *pi);
262 int pci_msi_enabled(struct pci_devinst *pi);
263 int pci_msix_enabled(struct pci_devinst *pi);
264 int pci_msix_table_bar(struct pci_devinst *pi);
265 int pci_msix_pba_bar(struct pci_devinst *pi);
266 int pci_msi_maxmsgnum(struct pci_devinst *pi);
267 int pci_parse_legacy_config(nvlist_t *nvl, const char *opt);
268 int pci_parse_slot(char *opt);
269 void pci_print_supported_devices(void);
270 void pci_populate_msicap(struct msicap *cap, int msgs, int nextptr);
271 int pci_emul_add_msixcap(struct pci_devinst *pi, int msgnum, int barnum);
272 int pci_emul_msix_twrite(struct pci_devinst *pi, uint64_t offset, int size,
273 uint64_t value);
274 uint64_t pci_emul_msix_tread(struct pci_devinst *pi, uint64_t offset, int size);
275 int pci_count_lintr(int bus);
276 void pci_walk_lintr(int bus, pci_lintr_cb cb, void *arg);
277 void pci_write_dsdt(void);
278 uint64_t pci_ecfg_base(void);
279 int pci_bus_configured(int bus);
280
281 static __inline void
pci_set_cfgdata8(struct pci_devinst * pi,int offset,uint8_t val)282 pci_set_cfgdata8(struct pci_devinst *pi, int offset, uint8_t val)
283 {
284 assert(offset <= PCI_REGMAX);
285 *(uint8_t *)(pi->pi_cfgdata + offset) = val;
286 }
287
288 static __inline void
pci_set_cfgdata16(struct pci_devinst * pi,int offset,uint16_t val)289 pci_set_cfgdata16(struct pci_devinst *pi, int offset, uint16_t val)
290 {
291 assert(offset <= (PCI_REGMAX - 1) && (offset & 1) == 0);
292 *(uint16_t *)(pi->pi_cfgdata + offset) = val;
293 }
294
295 static __inline void
pci_set_cfgdata32(struct pci_devinst * pi,int offset,uint32_t val)296 pci_set_cfgdata32(struct pci_devinst *pi, int offset, uint32_t val)
297 {
298 assert(offset <= (PCI_REGMAX - 3) && (offset & 3) == 0);
299 *(uint32_t *)(pi->pi_cfgdata + offset) = val;
300 }
301
302 static __inline uint8_t
pci_get_cfgdata8(struct pci_devinst * pi,int offset)303 pci_get_cfgdata8(struct pci_devinst *pi, int offset)
304 {
305 assert(offset <= PCI_REGMAX);
306 return (*(uint8_t *)(pi->pi_cfgdata + offset));
307 }
308
309 static __inline uint16_t
pci_get_cfgdata16(struct pci_devinst * pi,int offset)310 pci_get_cfgdata16(struct pci_devinst *pi, int offset)
311 {
312 assert(offset <= (PCI_REGMAX - 1) && (offset & 1) == 0);
313 return (*(uint16_t *)(pi->pi_cfgdata + offset));
314 }
315
316 static __inline uint32_t
pci_get_cfgdata32(struct pci_devinst * pi,int offset)317 pci_get_cfgdata32(struct pci_devinst *pi, int offset)
318 {
319 assert(offset <= (PCI_REGMAX - 3) && (offset & 3) == 0);
320 return (*(uint32_t *)(pi->pi_cfgdata + offset));
321 }
322
323 #endif /* _PCI_EMUL_H_ */
324