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Searched refs:efx_qword_t (Results 1 – 21 of 21) sorted by relevance

/illumos-gate/usr/src/uts/common/io/sfxge/common/
H A Defx_sram.c41 efx_qword_t qword; in efx_sram_buf_tbl_set()
207 __out efx_qword_t *eqp) in efx_sram_byte_increment_set()
214 for (index = 0; index < sizeof (efx_qword_t); index++) in efx_sram_byte_increment_set()
222 __out efx_qword_t *eqp) in efx_sram_all_the_same_set()
236 __out efx_qword_t *eqp) in efx_sram_bit_alternate_set()
249 __out efx_qword_t *eqp) in efx_sram_byte_alternate_set()
262 __out efx_qword_t *eqp) in efx_sram_byte_changing_set()
267 for (index = 0; index < sizeof (efx_qword_t); index++) { in efx_sram_byte_changing_set()
283 __out efx_qword_t *eqp) in efx_sram_bit_sweep_set()
289 EFX_CLEAR_QWORD_BIT(*eqp, (offset / sizeof (efx_qword_t)) % 64); in efx_sram_bit_sweep_set()
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H A Def10_tx.c60 efx_qword_t *dma_addr; in efx_mcdi_init_txq()
101 dma_addr = MCDI_IN2(req, efx_qword_t, INIT_TXQ_IN_DMA_ADDR); in efx_mcdi_init_txq()
192 efx_qword_t desc; in ef10_tx_qcreate()
323 efx_qword_t *eqp; in ef10_tx_qpio_write()
326 EFSYS_ASSERT(length % sizeof (efx_qword_t) == 0); in ef10_tx_qpio_write()
343 eqp = (efx_qword_t *)buffer; in ef10_tx_qpio_write()
347 write_offset += sizeof (efx_qword_t); in ef10_tx_qpio_write()
367 efx_qword_t pio_desc; in ef10_tx_qpio_post()
385 offset = id * sizeof (efx_qword_t); in ef10_tx_qpio_post()
437 efx_qword_t qword; in ef10_tx_qpost()
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H A Def10_ev.c53 __in efx_qword_t *eqp,
60 __in efx_qword_t *eqp,
67 __in efx_qword_t *eqp,
74 __in efx_qword_t *eqp,
81 __in efx_qword_t *eqp,
99 efx_qword_t *dma_addr; in efx_mcdi_init_evq()
151 dma_addr = MCDI_IN2(req, efx_qword_t, INIT_EVQ_IN_DMA_ADDR); in efx_mcdi_init_evq()
352 __in efx_qword_t data) in efx_mcdi_driver_event()
393 efx_qword_t event; in ef10_ev_qpost()
480 __in efx_qword_t *eqp, in ef10_ev_rx()
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H A Defx_ev.c319 efx_qword_t qword; in efx_ev_qpending()
323 offset = (count & eep->ee_mask) * sizeof (efx_qword_t); in efx_ev_qpending()
341 offset = (count & eep->ee_mask) * sizeof (efx_qword_t); in efx_ev_qprefetch()
453 __in efx_qword_t *eqp, in siena_ev_rx_not_ok()
543 __in efx_qword_t *eqp, in siena_ev_rx()
697 __in efx_qword_t *eqp, in siena_ev_tx()
744 __in efx_qword_t *eqp, in siena_ev_global()
758 __in efx_qword_t *eqp, in siena_ev_driver()
887 __in efx_qword_t *eqp, in siena_ev_drv_gen()
915 __in efx_qword_t *eqp, in siena_ev_mcdi()
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H A Defx_nic.c782 __out efx_qword_t *maskp) in efx_loopback_mask()
784 efx_qword_t mask; in efx_loopback_mask()
889 efx_qword_t mask; in efx_mcdi_get_loopback_modes()
890 efx_qword_t modes; in efx_mcdi_get_loopback_modes()
921 *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_SUGGESTED)); in efx_mcdi_get_loopback_modes()
923 modes = *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_100M); in efx_mcdi_get_loopback_modes()
927 modes = *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_1G); in efx_mcdi_get_loopback_modes()
931 modes = *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_10G); in efx_mcdi_get_loopback_modes()
940 *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_40G); in efx_mcdi_get_loopback_modes()
H A Dsiena_sram.c82 efx_qword_t qword; in siena_sram_test()
83 efx_qword_t verify; in siena_sram_test()
H A Dsiena_mac.c236 EFSYS_MEM_READQ((_esmp), (_field) * sizeof (efx_qword_t), _eqp)
245 efx_qword_t value; in siena_mac_stats_update()
246 efx_qword_t generation_start; in siena_mac_stats_update()
247 efx_qword_t generation_end; in siena_mac_stats_update()
H A Dmcdi_mon.h56 __in efx_qword_t *eqp,
H A Def10_rx.c54 efx_qword_t *dma_addr; in efx_mcdi_init_rxq()
83 dma_addr = MCDI_IN2(req, efx_qword_t, INIT_RXQ_IN_DMA_ADDR); in efx_mcdi_init_rxq()
646 efx_qword_t qword; in ef10_rx_qpost()
668 offset = id * sizeof (efx_qword_t); in ef10_rx_qpost()
H A Def10_mac.c420 EFSYS_MEM_READQ((_esmp), (_field) * sizeof (efx_qword_t), _eqp)
430 efx_qword_t value; in ef10_mac_stats_update()
431 efx_qword_t generation_start; in ef10_mac_stats_update()
432 efx_qword_t generation_end; in ef10_mac_stats_update()
H A Defx.h761 __out efx_qword_t *maskp);
1060 efx_qword_t enc_loopback_types[EFX_LINK_NMODES];
1465 __out efx_qword_t *eqp);
1554 #define EFX_EVQ_SIZE(_nevs) ((_nevs) * sizeof (efx_qword_t))
1857 #define EFX_RXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
1887 efx_qword_t ed_eq;
1950 #define EFX_TXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
H A Dsiena_impl.h306 __in efx_qword_t *eqp,
H A Def10_phy.c119 __in efx_qword_t *eqp, in ef10_phy_link_ev()
H A Defx_rx.c1008 efx_qword_t qword; in siena_rx_qpost()
1030 offset = id * sizeof (efx_qword_t); in siena_rx_qpost()
H A Defx_tx.c706 efx_qword_t qword; \
709 offset = id * sizeof (efx_qword_t); \
H A Dmcdi_mon.c256 __in efx_qword_t *eqp, in mcdi_mon_ev()
H A Dsiena_phy.c112 __in efx_qword_t *eqp, in siena_phy_link_ev()
H A Defx_types.h222 } efx_qword_t; typedef
233 efx_qword_t eo_qword[2];
H A Def10_impl.h560 __in efx_qword_t *eqp,
H A Defx_impl.h688 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *,
/illumos-gate/usr/src/uts/common/io/sfxge/
H A Defsys.h185 ASSERT(IS_P2ALIGNED(_offset, sizeof (efx_qword_t))); \
251 ASSERT(IS_P2ALIGNED(_offset, sizeof (efx_qword_t))); \
338 ASSERT(IS_P2ALIGNED(_offset, sizeof (efx_qword_t))); \
421 ASSERT(IS_P2ALIGNED(_offset, sizeof (efx_qword_t))); \
447 ASSERT(IS_P2ALIGNED(_offset, sizeof (efx_qword_t))); \