1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * Copyright 2026 Oxide Computer Company 14 */ 15 16 /* 17 * This file declares all constants and structures dealing with the 18 * physical ENA device. It is based on the ena_com code of the public 19 * Linux and FreeBSD drivers. While this file is based on the common 20 * code it doesn't share the same type names. Where it is useful, a 21 * "common" reference is added to include the name of the type as 22 * defined in the common code. 23 * 24 * The Linux driver defines enq_admin_aq_entry as the top-level type 25 * for admin command descriptors. From this type you can access the 26 * common bits shared by every descriptor (ena_admin_aq_common_desc) 27 * as well as the control buffer (ena_admin_ctrl_buff_info) which is 28 * present for _some_ commands. Other than that, this top-level type 29 * treats the rest of the data as an opaque array of unsigned 32-bit 30 * integers. Then, for each individual command, the Linux driver 31 * defines a dedicated type, each of which contains the following: 32 * 33 * 1. The common descriptor: ena_admin_aq_common_desc. 34 * 35 * 2. The optional control buffer desc: ena_admin_ctrl_buff_info. 36 * 37 * 3. The command-specific data. 38 * 39 * 4. Optional padding to make sure all commands are 64 bytes in size. 40 * 41 * Furthermore, there may be further common types for commands which 42 * are made up of several sub-commands, e.g. the get/set feature 43 * commands. 44 * 45 * Finally, when a command is passed to the common function for 46 * executing commands (ena_com_execute_admin_command()), it is cast as 47 * a pointer to the top-level type: ena_admin_aq_entry. 48 * 49 * This works for the Linux driver just fine, but it causes lots of 50 * repetition in the structure definitions and also means there is no 51 * easy way to determine all valid commands. This ENA driver has 52 * turned the Linux approach inside out -- the top-level type is a 53 * union of all possible commands: enahw_cmd_desc_t. Each command may 54 * then further sub-type via unions to represent its sub-commands. 55 * This same treatment was given to the response descriptor: 56 * enahw_resp_desc_t. 57 * 58 * What is the point of knowing all this? Well, when referencing the 59 * common type in the comment above the enahw_ type, you need to keep 60 * in mind that the Linux/common type will include all the common 61 * descriptor bits, whereas these types do not. 62 * 63 * The common code DOES NOT pack any of these structures, and thus 64 * neither do we. That means these structures all rely on natural 65 * compiler alignment, just as the common code does. In ena.c you will 66 * find CTASSERTs for many of these structures, to verify they are of 67 * the expected size. 68 */ 69 70 #ifndef _ENA_HW_H 71 #define _ENA_HW_H 72 73 #include <sys/ddi.h> 74 #include <sys/sunddi.h> 75 #include <sys/types.h> 76 #include <sys/debug.h> 77 #include <sys/ethernet.h> 78 79 /* 80 * The common code sets the upper limit of I/O queues to 128. In this 81 * case a "queue" is a SQ+CQ pair that forms a logical queue or ring 82 * for sending or receiving packets. Thus, at maximum, we may expect 83 * 128 Tx rings, and 128 Rx rings; though, practically speaking, the 84 * number of rings will often be limited by number of CPUs or 85 * available interrupts. 86 * 87 * common: ENA_MAX_NUM_IO_QUEUES 88 */ 89 #define ENAHW_MAX_NUM_IO_QUEUES 128 90 91 /* 92 * Generate a 32-bit bitmask where the bits between high (inclusive) 93 * and low (inclusive) are set to 1. 94 */ 95 #define GENMASK(h, l) (((~0U) - (1U << (l)) + 1) & (~0U >> (32 - 1 - (h)))) 96 97 /* 98 * Generate a 64-bit bitmask where bit b is set to 1. 99 */ 100 #define BIT(b) (1UL << (b)) 101 102 #define ENAHW_DMA_ADMINQ_ALIGNMENT 8 103 104 #define ENAHW_ADMIN_CQ_DESC_BUF_ALIGNMENT 8 105 #define ENAHW_ADMIN_SQ_DESC_BUF_ALIGNMENT 8 106 #define ENAHW_AENQ_DESC_BUF_ALIGNMENT 8 107 #define ENAHW_HOST_INFO_ALIGNMENT 8 108 #define ENAHW_HOST_INFO_ALLOC_SZ 4096 109 #define ENAHW_IO_CQ_DESC_BUF_ALIGNMENT 4096 110 #define ENAHW_IO_SQ_DESC_BUF_ALIGNMENT 8 111 112 /* 113 * BAR0 register offsets. 114 * 115 * Any register not defined in the common code was marked as a gap, 116 * using the hex address of the register as suffix to make it clear 117 * where the gaps are. 118 */ 119 #define ENAHW_REG_VERSION 0x0 120 #define ENAHW_REG_CONTROLLER_VERSION 0x4 121 #define ENAHW_REG_CAPS 0x8 122 #define ENAHW_REG_CAPS_EXT 0xc 123 #define ENAHW_REG_ASQ_BASE_LO 0x10 124 #define ENAHW_REG_ASQ_BASE_HI 0x14 125 #define ENAHW_REG_ASQ_CAPS 0x18 126 #define ENAHW_REG_GAP_1C 0x1c 127 #define ENAHW_REG_ACQ_BASE_LO 0x20 128 #define ENAHW_REG_ACQ_BASE_HI 0x24 129 #define ENAHW_REG_ACQ_CAPS 0x28 130 #define ENAHW_REG_ASQ_DB 0x2c 131 #define ENAHW_REG_ACQ_TAIL 0x30 132 #define ENAHW_REG_AENQ_CAPS 0x34 133 #define ENAHW_REG_AENQ_BASE_LO 0x38 134 #define ENAHW_REG_AENQ_BASE_HI 0x3c 135 #define ENAHW_REG_AENQ_HEAD_DB 0x40 136 #define ENAHW_REG_AENQ_TAIL 0x44 137 #define ENAHW_REG_GAP_48 0x48 138 #define ENAHW_REG_INTERRUPT_MASK 0x4c 139 #define ENAHW_REG_GAP_50 0x50 140 #define ENAHW_REG_DEV_CTL 0x54 141 #define ENAHW_REG_DEV_STS 0x58 142 #define ENAHW_REG_MMIO_REG_READ 0x5c 143 #define ENAHW_REG_MMIO_RESP_LO 0x60 144 #define ENAHW_REG_MMIO_RESP_HI 0x64 145 #define ENAHW_REG_RSS_IND_ENTRY_UPDATE 0x68 146 #define ENAHW_NUM_REGS ((ENAHW_REG_RSS_IND_ENTRY_UPDATE / 4) + 1) 147 148 /* 149 * Device Version (Register 0x0) 150 */ 151 #define ENAHW_DEV_MINOR_VSN_MASK 0xff 152 #define ENAHW_DEV_MAJOR_VSN_SHIFT 8 153 #define ENAHW_DEV_MAJOR_VSN_MASK 0xff00 154 155 #define ENAHW_DEV_MAJOR_VSN(vsn) \ 156 (((vsn) & ENAHW_DEV_MAJOR_VSN_MASK) >> ENAHW_DEV_MAJOR_VSN_SHIFT) 157 #define ENAHW_DEV_MINOR_VSN(vsn) \ 158 ((vsn) & ENAHW_DEV_MINOR_VSN_MASK) 159 160 /* 161 * Controller Version (Register 0x4) 162 */ 163 #define ENAHW_CTRL_SUBMINOR_VSN_MASK 0xff 164 #define ENAHW_CTRL_MINOR_VSN_SHIFT 8 165 #define ENAHW_CTRL_MINOR_VSN_MASK 0xff00 166 #define ENAHW_CTRL_MAJOR_VSN_SHIFT 16 167 #define ENAHW_CTRL_MAJOR_VSN_MASK 0xff0000 168 #define ENAHW_CTRL_IMPL_ID_SHIFT 24 169 #define ENAHW_CTRL_IMPL_ID_MASK 0xff000000 170 171 #define ENAHW_CTRL_MAJOR_VSN(vsn) \ 172 (((vsn) & ENAHW_CTRL_MAJOR_VSN_MASK) >> ENAHW_CTRL_MAJOR_VSN_SHIFT) 173 #define ENAHW_CTRL_MINOR_VSN(vsn) \ 174 (((vsn) & ENAHW_CTRL_MINOR_VSN_MASK) >> ENAHW_CTRL_MINOR_VSN_SHIFT) 175 #define ENAHW_CTRL_SUBMINOR_VSN(vsn) \ 176 ((vsn) & ENAHW_CTRL_SUBMINOR_VSN_MASK) 177 #define ENAHW_CTRL_IMPL_ID(vsn) \ 178 (((vsn) & ENAHW_CTRL_IMPL_ID_MASK) >> ENAHW_CTRL_IMPL_ID_SHIFT) 179 180 /* 181 * Device Caps (Register 0x8) 182 */ 183 #define ENAHW_CAPS_CONTIGUOUS_QUEUE_REQUIRED_MASK 0x1 184 #define ENAHW_CAPS_RESET_TIMEOUT_SHIFT 1 185 #define ENAHW_CAPS_RESET_TIMEOUT_MASK 0x3e 186 #define ENAHW_CAPS_RESET_TIMEOUT(v) \ 187 (((v) & ENAHW_CAPS_RESET_TIMEOUT_MASK) >> \ 188 ENAHW_CAPS_RESET_TIMEOUT_SHIFT) 189 #define ENAHW_CAPS_DMA_ADDR_WIDTH_SHIFT 8 190 #define ENAHW_CAPS_DMA_ADDR_WIDTH_MASK 0xff00 191 #define ENAHW_CAPS_DMA_ADDR_WIDTH(v) \ 192 (((v) & ENAHW_CAPS_DMA_ADDR_WIDTH_MASK) >> \ 193 ENAHW_CAPS_DMA_ADDR_WIDTH_SHIFT) 194 #define ENAHW_CAPS_ADMIN_CMD_TIMEOUT_SHIFT 16 195 #define ENAHW_CAPS_ADMIN_CMD_TIMEOUT_MASK 0xf0000 196 #define ENAHW_CAPS_ADMIN_CMD_TIMEOUT(v) \ 197 (((v) & ENAHW_CAPS_ADMIN_CMD_TIMEOUT_MASK) >> \ 198 ENAHW_CAPS_ADMIN_CMD_TIMEOUT_SHIFT) 199 200 typedef enum enahw_reset_reason_types { 201 ENAHW_RESET_NORMAL = 0, 202 ENAHW_RESET_KEEP_ALIVE_TO = 1, 203 ENAHW_RESET_ADMIN_TO = 2, 204 ENAHW_RESET_MISS_TX_CMPL = 3, 205 ENAHW_RESET_INV_RX_REQ_ID = 4, 206 ENAHW_RESET_INV_TX_REQ_ID = 5, 207 ENAHW_RESET_TOO_MANY_RX_DESCS = 6, 208 ENAHW_RESET_INIT_ERR = 7, 209 ENAHW_RESET_DRIVER_INVALID_STATE = 8, 210 ENAHW_RESET_OS_TRIGGER = 9, 211 ENAHW_RESET_OS_NETDEV_WD = 10, 212 ENAHW_RESET_SHUTDOWN = 11, 213 ENAHW_RESET_USER_TRIGGER = 12, 214 ENAHW_RESET_GENERIC = 13, 215 ENAHW_RESET_MISS_INTERRUPT = 14, 216 ENAHW_RESET_SUSPECTED_POLL_STARVATION = 15, 217 ENAHW_RESET_RX_DESCRIPTOR_MALFORMED = 16, 218 ENAHW_RESET_TX_DESCRIPTOR_MALFORMED = 17, 219 ENAHW_RESET_MISSING_ADMIN_INTERRUPT = 18, 220 ENAHW_RESET_DEVICE_REQUEST = 19, 221 ENAHW_RESET_LAST, 222 } enahw_reset_reason_t; 223 224 #define ENAHW_RESET_REASON_LSB_SHIFT 0 225 #define ENAHW_RESET_REASON_LSB_MASK 0xf 226 #define ENAHW_RESET_REASON_MSB_SHIFT 4 227 #define ENAHW_RESET_REASON_MSB_MASK 0xf0 228 #define ENAHW_RESET_REASON_LSB(v) \ 229 (((v) & ENAHW_RESET_REASON_LSB_MASK) >> ENAHW_RESET_REASON_LSB_SHIFT) 230 #define ENAHW_RESET_REASON_MSB(v) \ 231 (((v) & ENAHW_RESET_REASON_MSB_MASK) >> ENAHW_RESET_REASON_MSB_SHIFT) 232 233 /* 234 * Admin Submission Queue Caps (Register 0x18) 235 */ 236 #define ENAHW_ASQ_CAPS_DEPTH_MASK 0xffff 237 #define ENAHW_ASQ_CAPS_ENTRY_SIZE_SHIFT 16 238 #define ENAHW_ASQ_CAPS_ENTRY_SIZE_MASK 0xffff0000 239 240 #define ENAHW_ASQ_CAPS_DEPTH(x) ((x) & ENAHW_ASQ_CAPS_DEPTH_MASK) 241 242 #define ENAHW_ASQ_CAPS_ENTRY_SIZE(x) \ 243 (((x) << ENAHW_ASQ_CAPS_ENTRY_SIZE_SHIFT) & \ 244 ENAHW_ASQ_CAPS_ENTRY_SIZE_MASK) 245 246 /* 247 * Admin Completion Queue Caps (Register 0x28) 248 */ 249 #define ENAHW_ACQ_CAPS_DEPTH_MASK 0xffff 250 #define ENAHW_ACQ_CAPS_ENTRY_SIZE_SHIFT 16 251 #define ENAHW_ACQ_CAPS_ENTRY_SIZE_MASK 0xffff0000 252 253 #define ENAHW_ACQ_CAPS_DEPTH(x) ((x) & ENAHW_ACQ_CAPS_DEPTH_MASK) 254 255 #define ENAHW_ACQ_CAPS_ENTRY_SIZE(x) \ 256 (((x) << ENAHW_ACQ_CAPS_ENTRY_SIZE_SHIFT) & \ 257 ENAHW_ACQ_CAPS_ENTRY_SIZE_MASK) 258 259 /* 260 * Asynchronous Event Notification Queue Caps (Register 0x34) 261 */ 262 #define ENAHW_AENQ_CAPS_DEPTH_MASK 0xffff 263 #define ENAHW_AENQ_CAPS_ENTRY_SIZE_SHIFT 16 264 #define ENAHW_AENQ_CAPS_ENTRY_SIZE_MASK 0xffff0000 265 266 #define ENAHW_AENQ_CAPS_DEPTH(x) ((x) & ENAHW_AENQ_CAPS_DEPTH_MASK) 267 268 #define ENAHW_AENQ_CAPS_ENTRY_SIZE(x) \ 269 (((x) << ENAHW_AENQ_CAPS_ENTRY_SIZE_SHIFT) & \ 270 ENAHW_AENQ_CAPS_ENTRY_SIZE_MASK) 271 272 /* 273 * Interrupt Mask (Register 0x4c) 274 */ 275 #define ENAHW_INTR_UNMASK 0x0 276 #define ENAHW_INTR_MASK 0x1 277 278 /* 279 * Device Control (Register 0x54) 280 */ 281 #define ENAHW_DEV_CTL_DEV_RESET_MASK 0x1 282 #define ENAHW_DEV_CTL_AQ_RESTART_SHIFT 1 283 #define ENAHW_DEV_CTL_AQ_RESTART_MASK 0x2 284 #define ENAHW_DEV_CTL_QUIESCENT_SHIFT 2 285 #define ENAHW_DEV_CTL_QUIESCENT_MASK 0x4 286 #define ENAHW_DEV_CTL_IO_RESUME_SHIFT 3 287 #define ENAHW_DEV_CTL_IO_RESUME_MASK 0x8 288 #define ENAHW_DEV_CTL_RESET_REASON_EXT_SHIFT 24 289 #define ENAHW_DEV_CTL_RESET_REASON_EXT_MASK 0xf000000 290 #define ENAHW_DEV_CTL_RESET_REASON_SHIFT 28 291 #define ENAHW_DEV_CTL_RESET_REASON_MASK 0xf0000000 292 293 /* 294 * Device Status (Register 0x58) 295 */ 296 #define ENAHW_DEV_STS_READY_MASK 0x1 297 #define ENAHW_DEV_STS_AQ_RESTART_IN_PROGRESS_SHIFT 1 298 #define ENAHW_DEV_STS_AQ_RESTART_IN_PROGRESS_MASK 0x2 299 #define ENAHW_DEV_STS_AQ_RESTART_FINISHED_SHIFT 2 300 #define ENAHW_DEV_STS_AQ_RESTART_FINISHED_MASK 0x4 301 #define ENAHW_DEV_STS_RESET_IN_PROGRESS_SHIFT 3 302 #define ENAHW_DEV_STS_RESET_IN_PROGRESS_MASK 0x8 303 #define ENAHW_DEV_STS_RESET_FINISHED_SHIFT 4 304 #define ENAHW_DEV_STS_RESET_FINISHED_MASK 0x10 305 #define ENAHW_DEV_STS_FATAL_ERROR_SHIFT 5 306 #define ENAHW_DEV_STS_FATAL_ERROR_MASK 0x20 307 #define ENAHW_DEV_STS_QUIESCENT_STATE_IN_PROGRESS_SHIFT 6 308 #define ENAHW_DEV_STS_QUIESCENT_STATE_IN_PROGRESS_MASK 0x40 309 #define ENAHW_DEV_STS_QUIESCENT_STATE_ACHIEVED_SHIFT 7 310 #define ENAHW_DEV_STS_QUIESCENT_STATE_ACHIEVED_MASK 0x80 311 312 /* common: ena_admin_aenq_common_desc */ 313 typedef struct enahw_aenq_desc { 314 uint16_t ead_group; 315 uint16_t ead_syndrome; 316 uint8_t ead_flags; 317 uint8_t ead_rsvd1[3]; 318 uint32_t ead_ts_low; 319 uint32_t ead_ts_high; 320 321 union { 322 uint32_t raw[12]; 323 324 struct { 325 uint32_t flags; 326 } link_change; 327 328 struct { 329 uint32_t rx_drops_low; 330 uint32_t rx_drops_high; 331 uint32_t tx_drops_low; 332 uint32_t tx_drops_high; 333 uint32_t rx_overruns_low; 334 uint32_t rx_overruns_high; 335 } keep_alive; 336 } ead_payload; 337 } enahw_aenq_desc_t; 338 339 #define ENAHW_AENQ_DESC_PHASE_MASK BIT(0) 340 341 #define ENAHW_AENQ_DESC_PHASE(desc) \ 342 ((desc)->ead_flags & ENAHW_AENQ_DESC_PHASE_MASK) 343 344 #define ENAHW_AENQ_LINK_CHANGE_LINK_STATUS_MASK BIT(0) 345 346 /* 347 * Asynchronous Event Notification Queue groups. 348 * 349 * Note: These values represent the bit position of each feature as 350 * returned by ENAHW_FEAT_AENQ_CONFIG. We encode them this way so that 351 * they can double as an index into the AENQ handlers array. 352 * 353 * common: ena_admin_aenq_group 354 */ 355 typedef enum enahw_aenq_groups { 356 ENAHW_AENQ_GROUP_LINK_CHANGE = 0, 357 ENAHW_AENQ_GROUP_FATAL_ERROR = 1, 358 ENAHW_AENQ_GROUP_WARNING = 2, 359 ENAHW_AENQ_GROUP_NOTIFICATION = 3, 360 ENAHW_AENQ_GROUP_KEEP_ALIVE = 4, 361 ENAHW_AENQ_GROUP_REFRESH_CAPABILITIES = 5, 362 ENAHW_AENQ_GROUP_CONF_NOTIFICATIONS = 6, 363 ENAHW_AENQ_GROUP_DEVICE_REQUEST_RESET = 7, 364 ENAHW_AENQ_GROUPS_ARR_NUM = 8, 365 } enahw_aenq_groups_t; 366 367 /* 368 * The reason for ENAHW_AENQ_GROUP_NOFIFICATION. 369 * 370 * common: ena_admin_aenq_notification_syndrome 371 */ 372 typedef enum enahw_aenq_syndrome { 373 ENAHW_AENQ_SYNDROME_UPDATE_HINTS = 2, 374 } enahw_aenq_syndrome_t; 375 376 /* 377 * ENA devices use a 48-bit memory space. 378 * 379 * common: ena_common_mem_addr 380 */ 381 typedef struct enahw_addr { 382 uint32_t ea_low; 383 uint16_t ea_high; 384 uint16_t ea_rsvd; /* must be zero */ 385 } enahw_addr_t; 386 387 /* common: ena_admin_ctrl_buff_info */ 388 struct enahw_ctrl_buff { 389 uint32_t ecb_length; 390 enahw_addr_t ecb_addr; 391 }; 392 393 /* common: ena_admin_get_set_feature_common_desc */ 394 struct enahw_feat_common { 395 /* 396 * 1:0 Select which value you want. 397 * 398 * 0x1 = Current value. 399 * 0x3 = Default value. 400 * 401 * Note: Linux seems to set this to 0 to get the value, 402 * not sure if that's a bug or just another way to get the 403 * current value. 404 * 405 * 7:3 Reserved. 406 */ 407 uint8_t efc_flags; 408 409 /* An id from enahw_feature_id_t. */ 410 uint8_t efc_id; 411 412 /* 413 * Each feature is versioned, allowing upgrades to the feature 414 * set without breaking backwards compatibility. The driver 415 * uses this field to specify which version it supports 416 * (starting from zero). Linux doesn't document this very well 417 * and sets this value to 0 for most features. We define a set 418 * of macros, underneath the enahw_feature_id_t type, clearly 419 * documenting the version we support for each feature. 420 */ 421 uint8_t efc_version; 422 uint8_t efc_rsvd; 423 }; 424 425 /* common: ena_admin_get_feat_cmd */ 426 typedef struct enahw_cmd_get_feat { 427 struct enahw_ctrl_buff ecgf_ctrl_buf; 428 struct enahw_feat_common ecgf_comm; 429 uint32_t egcf_unused[11]; 430 } enahw_cmd_get_feat_t; 431 432 /* 433 * N.B. Linux sets efc_flags to 0 (via memset) when reading the 434 * current value, but the comments say it should be 0x1. We follow the 435 * comments. 436 */ 437 #define ENAHW_GET_FEAT_FLAGS_GET_CURR_VAL(desc) \ 438 ((desc)->ecgf_comm.efc_flags) |= 0x1 439 #define ENAHW_GET_FEAT_FLAGS_GET_DEF_VAL(desc) \ 440 ((desc)->ecgf_comm.efc_flags) |= 0x3 441 442 /* 443 * Set the MTU of the device. This value does not include the L2 444 * headers or trailers, only the payload. 445 * 446 * common: ena_admin_set_feature_mtu_desc 447 */ 448 typedef struct enahw_feat_mtu { 449 uint32_t efm_mtu; 450 } enahw_feat_mtu_t; 451 452 /* common: ena_admin_set_feature_host_attr_desc */ 453 typedef struct enahw_feat_host_attr { 454 enahw_addr_t efha_os_addr; 455 enahw_addr_t efha_debug_addr; 456 uint32_t efha_debug_sz; 457 } enahw_feat_host_attr_t; 458 459 /* 460 * ENAHW_FEAT_AENQ_CONFIG 461 * 462 * common: ena_admin_feature_aenq_desc 463 */ 464 typedef struct enahw_feat_aenq { 465 /* Bitmask of AENQ groups this device supports. */ 466 uint32_t efa_supported_groups; 467 468 /* Bitmask of AENQ groups currently enabled. */ 469 uint32_t efa_enabled_groups; 470 } enahw_feat_aenq_t; 471 472 /* 473 * ENAHW_FEAT_HW_TIMESTAMP 474 * 475 * common: ena_admin_feature_hw_ts_desc 476 */ 477 typedef struct enahw_feat_hw_timestamp { 478 uint8_t efhwts_version; 479 uint8_t efhwts_tx; 480 uint8_t efhwts_rx; 481 } enahw_feat_hw_timestamp_t; 482 483 /* 484 * Values for efhwts_tx and efhwts_rx in the above struct. 485 * 486 * common: ena_admin_hw_timestamp_tx_support / ena_admin_hw_timestamp_rx_support 487 */ 488 #define ENAHW_HW_TIMESTAMP_NONE 0 489 #define ENAHW_HW_TIMESTAMP_ALL_QUEUES 1 490 491 /* 492 * LLQ Header Location. 493 * 494 * Describes where the packet header resides relative to the 495 * descriptor list entries in the Low Latency Queue. 496 * 497 * common: ena_admin_llq_header_location 498 */ 499 typedef enum enahw_llq_header_location { 500 /* Header is in-line within the descriptor list entry */ 501 ENAHW_LLQ_HEADER_INLINE = BIT(0), 502 503 /* Header is in a separate ring (implies 16B descriptor entries) */ 504 ENAHW_LLQ_HEADER_SEPARATE_RING = BIT(1), 505 } enahw_llq_header_location_t; 506 507 /* 508 * LLQ Ring Entry Size. 509 * 510 * The size of each entry in the LLQ descriptor list in device memory. 511 * 512 * common: ena_admin_llq_ring_entry_size 513 */ 514 typedef enum enahw_llq_ring_entry_size { 515 ENAHW_LLQ_ENTRY_SIZE_128B = BIT(0), 516 ENAHW_LLQ_ENTRY_SIZE_192B = BIT(1), 517 ENAHW_LLQ_ENTRY_SIZE_256B = BIT(2), 518 } enahw_llq_ring_entry_size_t; 519 520 /* 521 * LLQ Number of Descriptors Before Header. 522 * 523 * When using inline header mode, the first entry contains some number 524 * of descriptors followed by the packet header. This enum specifies 525 * how many descriptors precede the header. 526 * 527 * common: ena_admin_llq_num_descs_before_header 528 */ 529 typedef enum enahw_llq_num_descs_before_header { 530 ENAHW_LLQ_NUM_DESCS_BEFORE_HEADER_0 = 0, 531 ENAHW_LLQ_NUM_DESCS_BEFORE_HEADER_1 = BIT(0), 532 ENAHW_LLQ_NUM_DESCS_BEFORE_HEADER_2 = BIT(1), 533 ENAHW_LLQ_NUM_DESCS_BEFORE_HEADER_4 = BIT(2), 534 ENAHW_LLQ_NUM_DESCS_BEFORE_HEADER_8 = BIT(3), 535 } enahw_llq_num_descs_before_header_t; 536 537 /* 538 * LLQ Descriptor Stride Control. 539 * 540 * Controls how descriptors beyond the first entry are laid out. With 541 * SINGLE_DESC_PER_ENTRY each subsequent entry holds one descriptor; 542 * with MULTIPLE_DESCS_PER_ENTRY they are packed contiguously. 543 * Only relevant for inline header mode. 544 * 545 * common: ena_admin_llq_stride_ctrl 546 */ 547 typedef enum enahw_llq_stride_ctrl { 548 ENAHW_LLQ_SINGLE_DESC_PER_ENTRY = BIT(0), 549 ENAHW_LLQ_MULTIPLE_DESCS_PER_ENTRY = BIT(1), 550 } enahw_llq_stride_ctrl_t; 551 552 /* 553 * LLQ Accelerated Mode Feature Flags. 554 * 555 * DISABLE_META_CACHING: The driver must send a meta descriptor with 556 * every packet rather than relying on the device caching meta 557 * information. 558 * 559 * LIMIT_TX_BURST: The device specifies a maximum burst size (in 560 * bytes) between doorbell writes. The driver must track how many 561 * bytes it has written and ring the doorbell before exceeding this 562 * limit. 563 * 564 * common: ena_admin_accel_mode_feat 565 */ 566 typedef enum enahw_llq_accel_mode_feat { 567 ENAHW_LLQ_ACCEL_MODE_DISABLE_META_CACHING = BIT(0), 568 ENAHW_LLQ_ACCEL_MODE_LIMIT_TX_BURST = BIT(1), 569 } enahw_llq_accel_mode_feat_t; 570 571 /* 572 * Accelerated LLQ mode - GET response. 573 * 574 * Returned by the device when querying the LLQ feature, indicating 575 * which accelerated mode features are supported and the maximum TX 576 * burst size. 577 * 578 * common: ena_admin_accel_mode_get 579 */ 580 typedef struct enahw_llq_accel_mode_get { 581 /* Bit field of enahw_llq_accel_mode_feat_t */ 582 uint16_t eamg_supported_flags; 583 584 /* Max bytes the driver may write to device memory before a doorbell */ 585 uint16_t eamg_max_tx_burst_size; 586 } enahw_llq_accel_mode_get_t; 587 588 /* 589 * Accelerated LLQ mode - SET request. 590 * 591 * Sent by the driver when configuring the LLQ feature, indicating 592 * which accelerated mode features to enable. 593 * 594 * common: ena_admin_accel_mode_set 595 */ 596 typedef struct enahw_llq_accel_mode_set { 597 /* Bit field of enahw_llq_accel_mode_feat_t */ 598 uint16_t eams_enabled_flags; 599 uint16_t eams_rsvd; 600 } enahw_llq_accel_mode_set_t; 601 602 /* 603 * Accelerated LLQ mode request/response union. 604 * 605 * Used in both GET_FEATURE and SET_FEATURE for LLQ. The 'get' variant 606 * is populated in responses; the 'set' variant is populated in 607 * requests. 608 * 609 * common: ena_admin_accel_mode_req 610 */ 611 typedef union enahw_llq_accel_mode { 612 uint32_t eam_raw[2]; 613 enahw_llq_accel_mode_get_t eam_get; 614 enahw_llq_accel_mode_set_t eam_set; 615 } enahw_llq_accel_mode_t; 616 617 /* 618 * Response to ENAHW_FEAT_LLQ. 619 * 620 * Describes the Low Latency Queue capabilities of the device. The 621 * _supported fields are populated on GET responses; the _enabled 622 * fields are populated by the driver on SET requests. 623 * 624 * common: ena_admin_feature_llq_desc 625 */ 626 typedef struct enahw_feat_llq { 627 uint32_t efllq_max_llq_num; 628 uint32_t efllq_max_llq_depth; 629 630 /* 631 * Bit field of enahw_llq_header_location_t. The locations the 632 * device supports (GET) or the driver has selected (SET). 633 */ 634 uint16_t efllq_header_location_ctrl_supported; 635 uint16_t efllq_header_location_ctrl_enabled; 636 637 /* 638 * Bit field of enahw_llq_ring_entry_size_t. The entry sizes 639 * the device supports (GET) or the driver has selected (SET). 640 */ 641 uint16_t efllq_entry_size_ctrl_supported; 642 uint16_t efllq_entry_size_ctrl_enabled; 643 644 /* 645 * Bit field of enahw_llq_num_descs_before_header_t. Valid 646 * only for inline header mode. The number of descriptors 647 * before the header the device supports (GET) or the driver 648 * has selected (SET). 649 */ 650 uint16_t efllq_desc_num_before_header_supported; 651 uint16_t efllq_desc_num_before_header_enabled; 652 653 /* 654 * Bit field of enahw_llq_stride_ctrl_t. Valid only for inline 655 * header mode. The stride control the device supports (GET) or 656 * the driver has selected (SET). 657 */ 658 uint16_t efllq_descs_stride_ctrl_supported; 659 uint16_t efllq_descs_stride_ctrl_enabled; 660 661 /* Feature version as reported by the device. */ 662 uint8_t efllq_feature_version; 663 664 /* 665 * The entry size recommended by the device, one of 666 * enahw_llq_ring_entry_size_t. Only valid on GET. 667 */ 668 uint8_t efllq_entry_size_recommended; 669 670 /* Max depth of wide LLQ, or 0 if not applicable. */ 671 uint16_t efllq_max_wide_llq_depth; 672 673 /* 674 * Accelerated LLQ mode capabilities (GET) or requested 675 * feature flags (SET). See enahw_llq_accel_mode_feat_t. 676 */ 677 enahw_llq_accel_mode_t efllq_accel_mode; 678 } enahw_feat_llq_t; 679 680 /* common: ena_admin_set_feat_cmd */ 681 typedef struct enahw_cmd_set_feat { 682 struct enahw_ctrl_buff ecsf_ctrl_buf; 683 struct enahw_feat_common ecsf_comm; 684 685 union { 686 uint32_t ecsf_raw[11]; 687 enahw_feat_host_attr_t ecsf_host_attr; 688 enahw_feat_mtu_t ecsf_mtu; 689 enahw_feat_aenq_t ecsf_aenq; 690 enahw_feat_hw_timestamp_t ecsf_hw_timestamp; 691 enahw_feat_llq_t ecsf_llq; 692 } ecsf_feat; 693 } enahw_cmd_set_feat_t; 694 695 /* 696 * Used to populate the host information buffer which the Nitro 697 * hypervisor supposedly uses for display, debugging, and possibly 698 * other purposes. 699 * 700 * common: ena_admin_host_info 701 */ 702 typedef struct enahw_host_info { 703 uint32_t ehi_os_type; 704 uint8_t ehi_os_dist_str[128]; 705 uint32_t ehi_os_dist; 706 uint8_t ehi_kernel_ver_str[32]; 707 uint32_t ehi_kernel_ver; 708 uint32_t ehi_driver_ver; 709 uint32_t ehi_supported_net_features[2]; 710 uint16_t ehi_ena_spec_version; 711 uint16_t ehi_bdf; 712 uint16_t ehi_num_cpus; 713 uint16_t ehi_rsvd; 714 uint32_t ehi_driver_supported_features; 715 } enahw_host_info_t; 716 717 #define ENAHW_HOST_INFO_MAJOR_MASK GENMASK(7, 0) 718 #define ENAHW_HOST_INFO_MINOR_SHIFT 8 719 #define ENAHW_HOST_INFO_MINOR_MASK GENMASK(15, 8) 720 #define ENAHW_HOST_INFO_SUB_MINOR_SHIFT 16 721 #define ENAHW_HOST_INFO_SUB_MINOR_MASK GENMASK(23, 16) 722 #define ENAHW_HOST_INFO_SPEC_MAJOR_SHIFT 8 723 #define ENAHW_HOST_INFO_MODULE_TYPE_SHIFT 24 724 #define ENAHW_HOST_INFO_MODULE_TYPE_MASK GENMASK(31, 24) 725 #define ENAHW_HOST_INFO_FUNCTION_MASK GENMASK(2, 0) 726 #define ENAHW_HOST_INFO_DEVICE_SHIFT 3 727 #define ENAHW_HOST_INFO_DEVICE_MASK GENMASK(7, 3) 728 #define ENAHW_HOST_INFO_BUS_SHIFT 8 729 #define ENAHW_HOST_INFO_BUS_MASK GENMASK(15, 8) 730 #define ENAHW_HOST_INFO_RX_OFFSET_SHIFT 1 731 #define ENAHW_HOST_INFO_RX_OFFSET_MASK BIT(1) 732 #define ENAHW_HOST_INFO_INTERRUPT_MODERATION_SHIFT 2 733 #define ENAHW_HOST_INFO_INTERRUPT_MODERATION_MASK BIT(2) 734 #define ENAHW_HOST_INFO_RX_BUF_MIRRORING_SHIFT 3 735 #define ENAHW_HOST_INFO_RX_BUF_MIRRORING_MASK BIT(3) 736 #define ENAHW_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_SHIFT 4 737 #define ENAHW_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_MASK BIT(4) 738 #define ENAHW_HOST_INFO_RX_PAGE_REUSE_SHIFT 6 739 #define ENAHW_HOST_INFO_RX_PAGE_REUSE_MASK BIT(6) 740 #define ENAHW_HOST_INFO_TX_IPV6_CSUM_OFFLOAD_SHIFT 7 741 #define ENAHW_HOST_INFO_TX_IPV6_CSUM_OFFLOAD_MASK BIT(7) 742 #define ENAHW_HOST_INFO_INFO_PHC_SHIFT 8 743 #define ENAHW_HOST_INFO_INFO_PHC_MASK BIT(8) 744 745 /* common: ena_admin_os_type */ 746 enum enahw_os_type { 747 ENAHW_OS_LINUX = 1, 748 ENAHW_OS_WIN = 2, 749 ENAHW_OS_DPDK = 3, 750 ENAHW_OS_FREEBSD = 4, 751 ENAHW_OS_IPXE = 5, 752 ENAHW_OS_ESXI = 6, 753 ENAHW_OS_MACOS = 7, 754 ENAHW_OS_GROUPS_NUM = 7, 755 }; 756 757 /* 758 * Create I/O Completion Queue 759 * 760 * A completion queue is where the device writes responses to I/O 761 * requests. The admin completion queue must be created before such a 762 * command can be issued, see ena_admin_cq_init(). 763 * 764 * common: ena_admin_aq_create_cq_cmd 765 */ 766 typedef struct enahw_cmd_create_cq { 767 /* 768 * 7-6 reserved 769 * 770 * 5 interrupt mode: when set the device sends an interrupt 771 * for each completion, otherwise the driver must poll 772 * the queue. 773 * 774 * 4-0 reserved 775 */ 776 uint8_t ecq_caps_1; 777 778 /* 779 * 7-5 reserved 780 * 781 * 4-0 CQ entry size (in words): the size of a single CQ entry 782 * in multiples of 32-bit words. 783 * 784 * NOTE: According to the common code the "valid" values 785 * are 4 or 8 -- this is incorrect. The valid values are 786 * 2 and 4. The common code does have an "extended" Rx 787 * completion descriptor, ena_eth_io_rx_cdesc_ext, that 788 * is 32 bytes and thus would use a value of 8, but it is 789 * not used by the Linux or FreeBSD drivers, so we do not 790 * bother with it. 791 * 792 * Type Bytes Value 793 * enahw_tx_cdesc_t 8 2 794 * enahw_rx_cdesc_t 16 4 795 */ 796 uint8_t ecq_caps_2; 797 798 /* The number of CQ entries, must be a power of 2. */ 799 uint16_t ecq_num_descs; 800 801 /* The MSI-X vector assigned to this CQ. */ 802 uint32_t ecq_msix_vector; 803 804 /* 805 * The CQ's physical base address. The CQ memory must be 806 * physically contiguous. 807 */ 808 enahw_addr_t ecq_addr; 809 } enahw_cmd_create_cq_t; 810 811 #define ENAHW_CMD_CREATE_CQ_INTERRUPT_MODE_ENABLED_SHIFT 5 812 #define ENAHW_CMD_CREATE_CQ_INTERRUPT_MODE_ENABLED_MASK (BIT(5)) 813 #define ENAHW_CMD_CREATE_CQ_DESC_SIZE_WORDS_MASK (GENMASK(4, 0)) 814 815 #define ENAHW_CMD_CREATE_CQ_INTERRUPT_MODE_ENABLE(cmd) \ 816 ((cmd)->ecq_caps_1 |= ENAHW_CMD_CREATE_CQ_INTERRUPT_MODE_ENABLED_MASK) 817 818 #define ENAHW_CMD_CREATE_CQ_DESC_SIZE_WORDS(cmd, val) \ 819 (((cmd)->ecq_caps_2) |= \ 820 ((val) & ENAHW_CMD_CREATE_CQ_DESC_SIZE_WORDS_MASK)) 821 822 /* 823 * Destroy Completion Queue 824 * 825 * common: ena_admin_aq_destroy_cq_cmd 826 */ 827 typedef struct enahw_cmd_destroy_cq { 828 uint16_t edcq_idx; 829 uint16_t edcq_rsvd; 830 } enahw_cmd_destroy_cq_t; 831 832 /* 833 * common: ena_admin_aq_create_sq_cmd 834 */ 835 typedef struct enahw_cmd_create_sq { 836 /* 837 * 7-5 direction: 0x1 = Tx, 0x2 = Rx 838 * 4-0 reserved 839 */ 840 uint8_t ecsq_dir; 841 uint8_t ecsq_rsvd1; 842 843 /* 844 * 7 reserved 845 * 846 * 6-4 completion policy: How are completion events generated. 847 * 848 * See enahw_completion_policy_type_t for a description of 849 * the various values. 850 * 851 * 3-0 placement policy: Where the descriptor ring and 852 * headers reside. 853 * 854 * See enahw_placement_policy_t for a description of the 855 * various values. 856 */ 857 uint8_t ecsq_caps_2; 858 859 /* 860 * 7-1 reserved 861 * 862 * 0 physically contiguous: When set indicates the descriptor 863 * ring memory is physically contiguous. 864 */ 865 uint8_t ecsq_caps_3; 866 867 /* 868 * The index of the associated Completion Queue (CQ). The CQ 869 * must be created before the SQ. 870 */ 871 uint16_t ecsq_cq_idx; 872 873 /* The number of descriptors in this SQ. */ 874 uint16_t ecsq_num_descs; 875 876 /* 877 * The base physical address of the SQ. This should not be set 878 * for LLQ. Must be page aligned. 879 */ 880 enahw_addr_t ecsq_base; 881 882 /* 883 * The physical address of the head write-back pointer. Valid 884 * only when the completion policy is set to one of the head 885 * write-back modes (0x2 or 0x3). Must be cacheline size 886 * aligned. 887 */ 888 enahw_addr_t ecsq_head_wb; 889 uint32_t ecsq_rsvdw2; 890 uint32_t ecsq_rsvdw3; 891 } enahw_cmd_create_sq_t; 892 893 typedef enum enahw_sq_direction { 894 ENAHW_SQ_DIRECTION_TX = 1, 895 ENAHW_SQ_DIRECTION_RX = 2, 896 } enahw_sq_direction_t; 897 898 typedef enum enahw_placement_policy { 899 /* Descriptors and headers are in host memory. */ 900 ENAHW_PLACEMENT_POLICY_HOST = 1, 901 902 /* 903 * Descriptors and headers are in device memory (a.k.a Low 904 * Latency Queue). 905 */ 906 ENAHW_PLACEMENT_POLICY_DEV = 3, 907 } enahw_placement_policy_t; 908 909 /* 910 * DESC: Write a CQ entry for each SQ descriptor. 911 * 912 * DESC_ON_DEMAND: Write a CQ entry when requested by the SQ descriptor. 913 * 914 * HEAD_ON_DEMAND: Update head pointer when requested by the SQ 915 * descriptor. 916 * 917 * HEAD: Update head pointer for each SQ descriptor. 918 * 919 */ 920 typedef enum enahw_completion_policy_type { 921 ENAHW_COMPLETION_POLICY_DESC = 0, 922 ENAHW_COMPLETION_POLICY_DESC_ON_DEMAND = 1, 923 ENAHW_COMPLETION_POLICY_HEAD_ON_DEMAND = 2, 924 ENAHW_COMPLETION_POLICY_HEAD = 3, 925 } enahw_completion_policy_type_t; 926 927 #define ENAHW_CMD_CREATE_SQ_DIR_SHIFT 5 928 #define ENAHW_CMD_CREATE_SQ_DIR_MASK GENMASK(7, 5) 929 #define ENAHW_CMD_CREATE_SQ_PLACEMENT_POLICY_MASK GENMASK(3, 0) 930 #define ENAHW_CMD_CREATE_SQ_COMPLETION_POLICY_SHIFT 4 931 #define ENAHW_CMD_CREATE_SQ_COMPLETION_POLICY_MASK GENMASK(6, 4) 932 #define ENAHW_CMD_CREATE_SQ_PHYSMEM_CONTIG_MASK BIT(0) 933 934 #define ENAHW_CMD_CREATE_SQ_DIR(cmd, val) \ 935 (((cmd)->ecsq_dir) |= (((val) << ENAHW_CMD_CREATE_SQ_DIR_SHIFT) & \ 936 ENAHW_CMD_CREATE_SQ_DIR_MASK)) 937 938 #define ENAHW_CMD_CREATE_SQ_PLACEMENT_POLICY(cmd, val) \ 939 (((cmd)->ecsq_caps_2) |= \ 940 ((val) & ENAHW_CMD_CREATE_SQ_PLACEMENT_POLICY_MASK)) 941 942 #define ENAHW_CMD_CREATE_SQ_COMPLETION_POLICY(cmd, val) \ 943 (((cmd)->ecsq_caps_2) |= \ 944 (((val) << ENAHW_CMD_CREATE_SQ_COMPLETION_POLICY_SHIFT) & \ 945 ENAHW_CMD_CREATE_SQ_COMPLETION_POLICY_MASK)) 946 947 #define ENAHW_CMD_CREATE_SQ_PHYSMEM_CONTIG(cmd) \ 948 ((cmd)->ecsq_caps_3 |= ENAHW_CMD_CREATE_SQ_PHYSMEM_CONTIG_MASK) 949 950 /* common: ena_admin_sq */ 951 typedef struct enahw_cmd_destroy_sq { 952 uint16_t edsq_idx; 953 uint8_t edsq_dir; /* Tx/Rx */ 954 uint8_t edsq_rsvd; 955 } enahw_cmd_destroy_sq_t; 956 957 #define ENAHW_CMD_DESTROY_SQ_DIR_SHIFT 5 958 #define ENAHW_CMD_DESTROY_SQ_DIR_MASK GENMASK(7, 5) 959 960 #define ENAHW_CMD_DESTROY_SQ_DIR(cmd, val) \ 961 (((cmd)->edsq_dir) |= (((val) << ENAHW_CMD_DESTROY_SQ_DIR_SHIFT) & \ 962 ENAHW_CMD_DESTROY_SQ_DIR_MASK)) 963 964 /* common: ena_admin_aq_get_stats_cmd */ 965 typedef struct enahw_cmd_get_stats { 966 struct enahw_ctrl_buff ecgs_ctrl_buf; 967 uint8_t ecgs_type; 968 uint8_t ecgs_scope; 969 uint16_t ecgs_rsvd; 970 uint16_t ecgs_queue_idx; 971 972 /* 973 * The device ID for which to query stats from. The sentinel 974 * value 0xFFFF indicates a query of the current device. 975 * According to the common docs, a "privileged device" may 976 * query stats for other ENA devices. However the definition 977 * of this "privilege device" is not expanded upon. 978 */ 979 uint16_t ecgs_device_id; 980 } enahw_cmd_get_stats_t; 981 982 /* Query the stats for my device. */ 983 #define ENAHW_CMD_GET_STATS_MY_DEVICE_ID 0xFFFF 984 985 /* 986 * BASIC: Returns enahw_resp_basic_stats. 987 * 988 * EXTENDED: According to the Linux documentation returns a buffer in 989 * "string format" with additional statistics per queue and per device ID. 990 * 991 * ENI: According to the Linux documentation it returns "extra HW 992 * stats for specific network interface". 993 * 994 * common: ena_admin_get_stats_type 995 */ 996 typedef enum enahw_get_stats_type { 997 ENAHW_GET_STATS_TYPE_BASIC = 0, 998 ENAHW_GET_STATS_TYPE_EXTENDED = 1, 999 ENAHW_GET_STATS_TYPE_ENI = 2, 1000 } enahw_get_stats_type_t; 1001 1002 /* common: ena_admin_get_stats_scope */ 1003 typedef enum enahw_get_stats_scope { 1004 ENAHW_GET_STATS_SCOPE_QUEUE = 0, 1005 ENAHW_GET_STATS_SCOPE_ETH = 1, 1006 } enahw_get_stats_scope_t; 1007 1008 /* common: ena_admin_aq_entry */ 1009 typedef struct enahw_cmd_desc { 1010 uint16_t ecd_cmd_id; 1011 uint8_t ecd_opcode; 1012 uint8_t ecd_flags; 1013 1014 union { 1015 uint32_t ecd_raw[15]; 1016 enahw_cmd_get_feat_t ecd_get_feat; 1017 enahw_cmd_set_feat_t ecd_set_feat; 1018 enahw_cmd_create_cq_t ecd_create_cq; 1019 enahw_cmd_destroy_cq_t ecd_destroy_cq; 1020 enahw_cmd_create_sq_t ecd_create_sq; 1021 enahw_cmd_destroy_sq_t ecd_destroy_sq; 1022 enahw_cmd_get_stats_t ecd_get_stats; 1023 } ecd_cmd; 1024 1025 } enahw_cmd_desc_t; 1026 1027 /* 1028 * top level commands that may be sent to the Admin Queue. 1029 * 1030 * common: ena_admin_aq_opcode 1031 */ 1032 typedef enum ena_cmd_opcode { 1033 ENAHW_CMD_NONE = 0, 1034 ENAHW_CMD_CREATE_SQ = 1, 1035 ENAHW_CMD_DESTROY_SQ = 2, 1036 ENAHW_CMD_CREATE_CQ = 3, 1037 ENAHW_CMD_DESTROY_CQ = 4, 1038 ENAHW_CMD_GET_FEATURE = 8, 1039 ENAHW_CMD_SET_FEATURE = 9, 1040 ENAHW_CMD_GET_STATS = 11, 1041 } enahw_cmd_opcode_t; 1042 1043 /* common: ENA_ADMIN_AQ_COMMON_DESC */ 1044 #define ENAHW_CMD_ID_MASK GENMASK(11, 0) 1045 #define ENAHW_CMD_PHASE_MASK BIT(0) 1046 1047 #define ENAHW_CMD_ID(desc, id) \ 1048 (((desc)->ecd_cmd_id) |= ((id) & ENAHW_CMD_ID_MASK)) 1049 1050 /* 1051 * Subcommands for ENA_ADMIN_{GET,SET}_FEATURE. 1052 * 1053 * common: ena_admin_aq_feature_id 1054 */ 1055 typedef enum enahw_feature_id { 1056 ENAHW_FEAT_DEVICE_ATTRIBUTES = 1, 1057 ENAHW_FEAT_MAX_QUEUES_NUM = 2, 1058 ENAHW_FEAT_HW_HINTS = 3, 1059 ENAHW_FEAT_LLQ = 4, 1060 ENAHW_FEAT_EXTRA_PROPERTIES_STRINGS = 5, 1061 ENAHW_FEAT_EXTRA_PROPERTIES_FLAGS = 6, 1062 ENAHW_FEAT_MAX_QUEUES_EXT = 7, 1063 ENAHW_FEAT_RSS_HASH_FUNCTION = 10, 1064 ENAHW_FEAT_STATELESS_OFFLOAD_CONFIG = 11, 1065 ENAHW_FEAT_RSS_INDIRECTION_TABLE_CONFIG = 12, 1066 ENAHW_FEAT_MTU = 14, 1067 ENAHW_FEAT_RSS_HASH_INPUT = 18, 1068 ENAHW_FEAT_INTERRUPT_MODERATION = 20, 1069 ENAHW_FEAT_AENQ_CONFIG = 26, 1070 ENAHW_FEAT_LINK_CONFIG = 27, 1071 ENAHW_FEAT_HOST_ATTR_CONFIG = 28, 1072 ENAHW_FEAT_PHC_CONFIG = 29, 1073 ENAHW_FEAT_FLOW_STEERING_CONFIG = 30, 1074 ENAHW_FEAT_HW_TIMESTAMP = 31, 1075 ENAHW_FEAT_NUM = 32, 1076 } enahw_feature_id_t; 1077 1078 /* 1079 * Device capabilities. 1080 * 1081 * common: ena_admin_aq_caps_id 1082 */ 1083 typedef enum enahw_capability_id { 1084 ENAHW_CAP_ENI_STATS = 0, 1085 ENAHW_CAP_ENA_SRD_INFO = 1, 1086 ENAHW_CAP_CUSTOMER_METRICS = 2, 1087 ENAHW_CAP_EXTENDED_RESET_REASONS = 3, 1088 ENAHW_CAP_CDESC_MBZ = 4, 1089 ENAHW_CAP_NUM 1090 } enahw_capability_id_t; 1091 1092 /* 1093 * The following macros define the maximum version we support for each 1094 * feature. These are the feature versions we use to communicate with 1095 * the feature command. Linux has these values spread throughout the 1096 * code at the various callsites of ena_com_get_feature(). We choose 1097 * to centralize our feature versions to make it easier to audit. 1098 */ 1099 #define ENAHW_FEAT_DEVICE_ATTRIBUTES_VER 0 1100 #define ENAHW_FEAT_MAX_QUEUES_NUM_VER 0 1101 #define ENAHW_FEAT_HW_HINTS_VER 0 1102 #define ENAHW_FEAT_LLQ_VER 1 1103 #define ENAHW_FEAT_EXTRA_PROPERTIES_STRINGS_VER 0 1104 #define ENAHW_FEAT_EXTRA_PROPERTIES_FLAGS_VER 0 1105 #define ENAHW_FEAT_MAX_QUEUES_EXT_VER 1 1106 #define ENAHW_FEAT_RSS_HASH_FUNCTION_VER 0 1107 #define ENAHW_FEAT_STATELESS_OFFLOAD_CONFIG_VER 0 1108 #define ENAHW_FEAT_RSS_INDIRECTION_TABLE_CONFIG_VER 0 1109 #define ENAHW_FEAT_MTU_VER 0 1110 #define ENAHW_FEAT_RSS_HASH_INPUT_VER 0 1111 #define ENAHW_FEAT_INTERRUPT_MODERATION_VER 0 1112 #define ENAHW_FEAT_AENQ_CONFIG_VER 0 1113 #define ENAHW_FEAT_LINK_CONFIG_VER 0 1114 #define ENAHW_FEAT_HOST_ATTR_CONFIG_VER 0 1115 #define ENAHW_FEAT_HW_TIMESTAMP_VER 0 1116 1117 /* common: ena_admin_link_types */ 1118 typedef enum enahw_link_speeds { 1119 ENAHW_LINK_SPEED_1G = 0x1, 1120 ENAHW_LINK_SPEED_2_HALF_G = 0x2, 1121 ENAHW_LINK_SPEED_5G = 0x4, 1122 ENAHW_LINK_SPEED_10G = 0x8, 1123 ENAHW_LINK_SPEED_25G = 0x10, 1124 ENAHW_LINK_SPEED_40G = 0x20, 1125 ENAHW_LINK_SPEED_50G = 0x40, 1126 ENAHW_LINK_SPEED_100G = 0x80, 1127 ENAHW_LINK_SPEED_200G = 0x100, 1128 ENAHW_LINK_SPEED_400G = 0x200, 1129 } enahw_link_speeds_t; 1130 1131 /* 1132 * Response to ENAHW_FEAT_HW_HINTS. 1133 * 1134 * Hints from the device to the driver about what values to use for 1135 * various communications between the two. A value of 0 indicates 1136 * there is no hint and the driver should provide its own default. All 1137 * timeout values are in milliseconds. 1138 * 1139 * common: ena_admin_ena_hw_hints 1140 */ 1141 1142 #define ENAHW_HINTS_NO_TIMEOUT 0xffff 1143 1144 typedef struct enahw_device_hints { 1145 /* 1146 * The amount of time the driver should wait for an MMIO read 1147 * reply before giving up and returning an error. 1148 */ 1149 uint16_t edh_mmio_read_timeout; 1150 1151 /* 1152 * If the driver has not seen an AENQ keep alive in this 1153 * timeframe, then consider the device hung and perform a 1154 * reset. 1155 * common: driver_watchdog_timeout 1156 */ 1157 uint16_t edh_keep_alive_timeout; 1158 1159 /* 1160 * The timeperiod in which we expect a Tx to report 1161 * completion, otherwise it is considered "missed". Initiate a 1162 * device reset when the number of missed completions is 1163 * greater than the threshold. 1164 */ 1165 uint16_t edh_tx_comp_timeout; 1166 uint16_t edh_missed_tx_reset_threshold; 1167 1168 /* 1169 * The timeperiod in which we expect an admin command to 1170 * report completion. 1171 */ 1172 uint16_t edh_admin_comp_timeout; 1173 1174 /* 1175 * Used by Linux to set the netdevice 'watchdog_timeo' value. 1176 * This value is used by the networking stack to determine 1177 * when a pending transmission has stalled. This is similar to 1178 * the keep alive timeout, except its viewing progress from 1179 * the perspective of the network stack itself. This difference 1180 * is subtle but important: the device could be in a state 1181 * where it has a functioning keep alive heartbeat, but has a 1182 * stuck Tx queue impeding forward progress of the networking 1183 * stack (which in many cases results in a scenario 1184 * indistinguishable from a complete host hang). 1185 * 1186 * The mac layer does not currently provide such 1187 * functionality, though it could and should be extended to 1188 * support such a feature. 1189 */ 1190 uint16_t edh_net_wd_timeout; 1191 1192 /* 1193 * The maximum number of cookies/segments allowed in a DMA 1194 * scatter-gather list. 1195 */ 1196 uint16_t edh_max_tx_sgl; 1197 uint16_t edh_max_rx_sgl; 1198 1199 uint16_t reserved[8]; 1200 } enahw_device_hints_t; 1201 1202 /* 1203 * Response to ENAHW_FEAT_DEVICE_ATTRIBUTES. 1204 * 1205 * common: ena_admin_device_attr_feature_desc 1206 */ 1207 typedef struct enahw_feat_dev_attr { 1208 uint32_t efda_impl_id; 1209 uint32_t efda_device_version; 1210 1211 /* 1212 * Bitmap representing supported get/set feature subcommands 1213 * (enahw_feature_id). 1214 */ 1215 uint32_t efda_supported_features; 1216 1217 /* 1218 * Bitmap representing device capabilities. 1219 * (enahw_capability_id) 1220 */ 1221 uint32_t efda_capabilities; 1222 1223 /* Number of bits used for physical/virtual address. */ 1224 uint32_t efda_phys_addr_width; 1225 uint32_t efda_virt_addr_with; 1226 1227 /* The unicast MAC address in network byte order. */ 1228 uint8_t efda_mac_addr[6]; 1229 uint8_t efda_rsvd2[2]; 1230 uint32_t efda_max_mtu; 1231 } enahw_feat_dev_attr_t; 1232 1233 /* 1234 * Response to ENAHW_FEAT_MAX_QUEUES_NUM. 1235 * 1236 * common: ena_admin_queue_feature_desc 1237 */ 1238 typedef struct enahw_feat_max_queue { 1239 uint32_t efmq_max_sq_num; 1240 uint32_t efmq_max_sq_depth; 1241 uint32_t efmq_max_cq_num; 1242 uint32_t efmq_max_cq_depth; 1243 uint32_t efmq_max_legacy_llq_num; 1244 uint32_t efmq_max_legacy_llq_depth; 1245 uint32_t efmq_max_header_size; 1246 1247 /* 1248 * The maximum number of descriptors a single Tx packet may 1249 * span. This includes the meta descriptor. 1250 */ 1251 uint16_t efmq_max_per_packet_tx_descs; 1252 1253 /* 1254 * The maximum number of descriptors a single Rx packet may span. 1255 */ 1256 uint16_t efmq_max_per_packet_rx_descs; 1257 } enahw_feat_max_queue_t; 1258 1259 /* 1260 * Response to ENAHW_FEAT_MAX_QUEUES_EXT. 1261 * 1262 * common: ena_admin_queue_ext_feature_desc 1263 */ 1264 typedef struct enahw_feat_max_queue_ext { 1265 uint8_t efmqe_version; 1266 uint8_t efmqe_rsvd[3]; 1267 1268 uint32_t efmqe_max_tx_sq_num; 1269 uint32_t efmqe_max_tx_cq_num; 1270 uint32_t efmqe_max_rx_sq_num; 1271 uint32_t efmqe_max_rx_cq_num; 1272 uint32_t efmqe_max_tx_sq_depth; 1273 uint32_t efmqe_max_tx_cq_depth; 1274 uint32_t efmqe_max_rx_sq_depth; 1275 uint32_t efmqe_max_rx_cq_depth; 1276 uint32_t efmqe_max_tx_header_size; 1277 1278 /* 1279 * The maximum number of descriptors a single Tx packet may 1280 * span. This includes the meta descriptor. 1281 */ 1282 uint16_t efmqe_max_per_packet_tx_descs; 1283 1284 /* 1285 * The maximum number of descriptors a single Rx packet may span. 1286 */ 1287 uint16_t efmqe_max_per_packet_rx_descs; 1288 } enahw_feat_max_queue_ext_t; 1289 1290 /* 1291 * Response to ENA_ADMIN_LINK_CONFIG. 1292 * 1293 * common: ena_admin_get_feature_link_desc 1294 */ 1295 typedef struct enahw_feat_link_conf { 1296 /* Link speed in Mbit/s. */ 1297 uint32_t eflc_speed; 1298 1299 /* Bit field of enahw_link_speeds_t. */ 1300 uint32_t eflc_supported; 1301 1302 /* 1303 * 31-2: reserved 1304 * 1: duplex - Full Duplex 1305 * 0: autoneg 1306 */ 1307 uint32_t eflc_flags; 1308 } enahw_feat_link_conf_t; 1309 1310 #define ENAHW_FEAT_LINK_CONF_AUTONEG_MASK BIT(0) 1311 #define ENAHW_FEAT_LINK_CONF_DUPLEX_SHIFT 1 1312 #define ENAHW_FEAT_LINK_CONF_DUPLEX_MASK BIT(1) 1313 1314 #define ENAHW_FEAT_LINK_CONF_AUTONEG(f) \ 1315 ((f)->eflc_flags & ENAHW_FEAT_LINK_CONF_AUTONEG_MASK) 1316 1317 #define ENAHW_FEAT_LINK_CONF_FULL_DUPLEX(f) \ 1318 ((((f)->eflc_flags & ENAHW_FEAT_LINK_CONF_DUPLEX_MASK) >> \ 1319 ENAHW_FEAT_LINK_CONF_DUPLEX_SHIFT) == 1) 1320 1321 /* 1322 * Response to ENAHW_FEAT_STATELESS_OFFLOAD_CONFIG. 1323 * 1324 * common: ena_admin_feature_offload_desc 1325 */ 1326 typedef struct enahw_feat_offload { 1327 /* 1328 * 0 : Tx IPv4 Header Checksum 1329 * 1 : Tx L4/IPv4 Partial Checksum 1330 * 1331 * The L4 checksum field should be initialized with pseudo 1332 * header checksum. 1333 * 1334 * 2 : Tx L4/IPv4 Checksum Full 1335 * 3 : Tx L4/IPv6 Partial Checksum 1336 * 1337 * The L4 checksum field should be initialized with pseudo 1338 * header checksum. 1339 * 1340 * 4 : Tx L4/IPv6 Checksum Full 1341 * 5 : TCP/IPv4 LSO (aka TSO) 1342 * 6 : TCP/IPv6 LSO (aka TSO) 1343 * 7 : LSO ECN 1344 */ 1345 uint32_t efo_tx; 1346 1347 /* 1348 * Receive side supported stateless offload. 1349 * 1350 * 0 : Rx IPv4 Header Checksum 1351 * 1 : Rx TCP/UDP + IPv4 Full Checksum 1352 * 2 : Rx TCP/UDP + IPv6 Full Checksum 1353 * 3 : Rx hash calculation 1354 */ 1355 uint32_t efo_rx_supported; 1356 1357 /* Linux seems to only check rx_supported. */ 1358 uint32_t efo_rx_enabled; 1359 } enahw_feat_offload_t; 1360 1361 /* Feature Offloads */ 1362 #define ENAHW_FEAT_OFFLOAD_TX_L3_IPV4_CSUM_MASK BIT(0) 1363 #define ENAHW_FEAT_OFFLOAD_TX_L4_IPV4_CSUM_PART_SHIFT 1 1364 #define ENAHW_FEAT_OFFLOAD_TX_L4_IPV4_CSUM_PART_MASK BIT(1) 1365 #define ENAHW_FEAT_OFFLOAD_TX_L4_IPV4_CSUM_FULL_SHIFT 2 1366 #define ENAHW_FEAT_OFFLOAD_TX_L4_IPV4_CSUM_FULL_MASK BIT(2) 1367 #define ENAHW_FEAT_OFFLOAD_TX_L4_IPV6_CSUM_PART_SHIFT 3 1368 #define ENAHW_FEAT_OFFLOAD_TX_L4_IPV6_CSUM_PART_MASK BIT(3) 1369 #define ENAHW_FEAT_OFFLOAD_TX_L4_IPV6_CSUM_FULL_SHIFT 4 1370 #define ENAHW_FEAT_OFFLOAD_TX_L4_IPV6_CSUM_FULL_MASK BIT(4) 1371 #define ENAHW_FEAT_OFFLOAD_TSO_IPV4_SHIFT 5 1372 #define ENAHW_FEAT_OFFLOAD_TSO_IPV4_MASK BIT(5) 1373 #define ENAHW_FEAT_OFFLOAD_TSO_IPV6_SHIFT 6 1374 #define ENAHW_FEAT_OFFLOAD_TSO_IPV6_MASK BIT(6) 1375 #define ENAHW_FEAT_OFFLOAD_TSO_ECN_SHIFT 7 1376 #define ENAHW_FEAT_OFFLOAD_TSO_ECN_MASK BIT(7) 1377 #define ENAHW_FEAT_OFFLOAD_RX_L3_IPV4_CSUM_MASK BIT(0) 1378 #define ENAHW_FEAT_OFFLOAD_RX_L4_IPV4_CSUM_SHIFT 1 1379 #define ENAHW_FEAT_OFFLOAD_RX_L4_IPV4_CSUM_MASK BIT(1) 1380 #define ENAHW_FEAT_OFFLOAD_RX_L4_IPV6_CSUM_SHIFT 2 1381 #define ENAHW_FEAT_OFFLOAD_RX_L4_IPV6_CSUM_MASK BIT(2) 1382 #define ENAHW_FEAT_OFFLOAD_RX_HASH_SHIFT 3 1383 #define ENAHW_FEAT_OFFLOAD_RX_HASH_MASK BIT(3) 1384 1385 #define ENAHW_FEAT_OFFLOAD_TX_L3_IPV4_CSUM(f) \ 1386 (((f)->efo_tx & ENAHW_FEAT_OFFLOAD_TX_L3_IPV4_CSUM_MASK) != 0) 1387 1388 #define ENAHW_FEAT_OFFLOAD_TX_L4_IPV4_CSUM_PART(f) \ 1389 (((f)->efo_tx & ENAHW_FEAT_OFFLOAD_TX_L4_IPV4_CSUM_PART_MASK) != 0) 1390 1391 #define ENAHW_FEAT_OFFLOAD_TX_L4_IPV4_CSUM_FULL(f) \ 1392 (((f)->efo_tx & ENAHW_FEAT_OFFLOAD_TX_L4_IPV4_CSUM_FULL_MASK) != 0) 1393 1394 #define ENAHW_FEAT_OFFLOAD_TSO_IPV4(f) \ 1395 (((f)->efo_tx & ENAHW_FEAT_OFFLOAD_TSO_IPV4_MASK) != 0) 1396 1397 #define ENAHW_FEAT_OFFLOAD_TX_L4_IPV6_CSUM_PART(f) \ 1398 (((f)->efo_tx & ENAHW_FEAT_OFFLOAD_TX_L4_IPV6_CSUM_PART_MASK) != 0) 1399 1400 #define ENAHW_FEAT_OFFLOAD_TX_L4_IPV6_CSUM_FULL(f) \ 1401 (((f)->efo_tx & ENAHW_FEAT_OFFLOAD_TX_L4_IPV6_CSUM_FULL_MASK) != 0) 1402 1403 #define ENAHW_FEAT_OFFLOAD_TSO_IPV6(f) \ 1404 (((f)->efo_tx & ENAHW_FEAT_OFFLOAD_TSO_IPV6_MASK) != 0) 1405 1406 #define ENAHW_FEAT_OFFLOAD_RX_L3_IPV4_CSUM(f) \ 1407 (((f)->efo_rx_supported & ENAHW_FEAT_OFFLOAD_RX_L3_IPV4_CSUM_MASK) != 0) 1408 1409 #define ENAHW_FEAT_OFFLOAD_RX_L4_IPV4_CSUM(f) \ 1410 (((f)->efo_rx_supported & ENAHW_FEAT_OFFLOAD_RX_L4_IPV4_CSUM_MASK) != 0) 1411 1412 #define ENAHW_FEAT_OFFLOAD_RX_L4_IPV6_CSUM(f) \ 1413 (((f)->efo_rx_supported & ENAHW_FEAT_OFFLOAD_RX_L4_IPV6_CSUM_MASK) != 0) 1414 1415 typedef union enahw_resp_get_feat { 1416 uint32_t ergf_raw[14]; 1417 enahw_feat_dev_attr_t ergf_dev_attr; 1418 enahw_feat_max_queue_t ergf_max_queue; 1419 enahw_feat_max_queue_ext_t ergf_max_queue_ext; 1420 enahw_feat_aenq_t ergf_aenq; 1421 enahw_feat_link_conf_t ergf_link_conf; 1422 enahw_feat_offload_t ergf_offload; 1423 enahw_device_hints_t ergf_hints; 1424 enahw_feat_llq_t ergf_llq; 1425 } enahw_resp_get_feat_u; 1426 1427 /* 1428 * common: ena_admin_acq_create_cq_resp_desc 1429 */ 1430 typedef struct enahw_resp_create_cq { 1431 /* 1432 * The hardware's index for this queue. 1433 */ 1434 uint16_t ercq_idx; 1435 1436 /* 1437 * Apparently the number of descriptors granted may be 1438 * different than that requested. 1439 */ 1440 uint16_t ercq_actual_num_descs; 1441 uint32_t ercq_numa_node_reg_offset; 1442 /* CQ doorbell register - no longer supported by any ENA adapter */ 1443 uint32_t ercq_head_db_reg_offset; 1444 uint32_t ercq_interrupt_mask_reg_offset; /* stop intr */ 1445 } enahw_resp_create_cq_t; 1446 1447 /* common: ena_admin_acq_create_sq_resp_desc */ 1448 typedef struct enahw_resp_create_sq { 1449 uint16_t ersq_idx; 1450 uint16_t ersq_rsvdw1; 1451 uint32_t ersq_db_reg_offset; 1452 uint32_t ersq_llq_descs_reg_offset; 1453 uint32_t ersq_llq_headers_reg_offset; 1454 } enahw_resp_create_sq_t; 1455 1456 /* common: ena_admin_basic_stats */ 1457 typedef struct enahw_resp_basic_stats { 1458 uint32_t erbs_tx_bytes_low; 1459 uint32_t erbs_tx_bytes_high; 1460 uint32_t erbs_tx_pkts_low; 1461 uint32_t erbs_tx_pkts_high; 1462 uint32_t erbs_rx_bytes_low; 1463 uint32_t erbs_rx_bytes_high; 1464 uint32_t erbs_rx_pkts_low; 1465 uint32_t erbs_rx_pkts_high; 1466 uint32_t erbs_rx_drops_low; 1467 uint32_t erbs_rx_drops_high; 1468 uint32_t erbs_tx_drops_low; 1469 uint32_t erbs_tx_drops_high; 1470 uint32_t erbs_rx_overruns_low; 1471 uint32_t erbs_rx_overruns_high; 1472 } enahw_resp_basic_stats_t; 1473 1474 /* common: ena_admin_eni_stats */ 1475 typedef struct enahw_resp_eni_stats { 1476 /* 1477 * The number of inbound packets dropped due to aggregate 1478 * inbound bandwidth allowance being exceeded. 1479 */ 1480 uint64_t eres_bw_in_exceeded; 1481 1482 /* 1483 * The number of outbound packets dropped due to aggregated outbound 1484 * bandwidth allowance being exceeded. 1485 */ 1486 uint64_t eres_bw_out_exceeded; 1487 1488 /* 1489 * The number of packets dropped due to the Packets Per Second 1490 * allowance being exceeded. 1491 */ 1492 uint64_t eres_pps_exceeded; 1493 1494 /* 1495 * The number of packets dropped due to connection tracking 1496 * allowance being exceeded and leading to failure in 1497 * establishment of new connections. 1498 */ 1499 uint64_t eres_conns_exceeded; 1500 1501 /* 1502 * The number of packets dropped due to linklocal packet rate 1503 * allowance being exceeded. 1504 */ 1505 uint64_t eres_linklocal_exceeded; 1506 } enahw_resp_eni_stats_t; 1507 1508 /* 1509 * common: ena_admin_acq_entry 1510 */ 1511 typedef struct enahw_resp_desc { 1512 /* The index of the completed command. */ 1513 uint16_t erd_cmd_id; 1514 1515 /* The status of the command (enahw_resp_status_t). */ 1516 uint8_t erd_status; 1517 1518 /* 1519 * 7-1 Reserved 1520 * 0 Phase 1521 */ 1522 uint8_t erd_flags; 1523 1524 /* Extended status. */ 1525 uint16_t erd_ext_status; 1526 1527 /* 1528 * The AQ entry (enahw_cmd_desc) index which has been consumed 1529 * by the device and can be reused. However, this field is not 1530 * used in the other drivers, and it seems to be redundant 1531 * with the erd_idx field. 1532 */ 1533 uint16_t erd_sq_head_idx; 1534 1535 union { 1536 uint32_t raw[14]; 1537 enahw_resp_get_feat_u erd_get_feat; 1538 enahw_resp_create_cq_t erd_create_cq; 1539 /* destroy_cq: No command-specific response. */ 1540 enahw_resp_create_sq_t erd_create_sq; 1541 /* destroy_sq: No command-specific response. */ 1542 enahw_resp_basic_stats_t erd_basic_stats; 1543 enahw_resp_eni_stats_t erd_eni_stats; 1544 } erd_resp; 1545 } enahw_resp_desc_t; 1546 1547 /* common: ENA_ADMIN_ACQ_COMMON_DESC */ 1548 #define ENAHW_RESP_CMD_ID_MASK GENMASK(11, 0) 1549 #define ENAHW_RESP_PHASE_MASK 0x1 1550 1551 #define ENAHW_RESP_CMD_ID(desc) \ 1552 (((desc)->erd_cmd_id) & ENAHW_RESP_CMD_ID_MASK) 1553 1554 /* 1555 * The response status of an Admin Queue command. 1556 * 1557 * common: ena_admin_aq_completion_status 1558 */ 1559 typedef enum enahw_resp_status { 1560 ENAHW_RESP_SUCCESS = 0, 1561 ENAHW_RESP_RESOURCE_ALLOCATION_FAILURE = 1, 1562 ENAHW_RESP_BAD_OPCODE = 2, 1563 ENAHW_RESP_UNSUPPORTED_OPCODE = 3, 1564 ENAHW_RESP_MALFORMED_REQUEST = 4, 1565 /* 1566 * At this place in the common code it mentions that there is 1567 * "additional status" in the response descriptor's 1568 * erd_ext_status field. As the common code never actually 1569 * uses this field it's hard to know the exact meaning of the 1570 * comment. My best guess is the illegal parameter error 1571 * stores additional context in the erd_ext_status field. But 1572 * how to interpret that additional context is anyone's guess. 1573 */ 1574 ENAHW_RESP_ILLEGAL_PARAMETER = 5, 1575 ENAHW_RESP_UNKNOWN_ERROR = 6, 1576 ENAHW_RESP_RESOURCE_BUSY = 7, 1577 } enahw_resp_status_t; 1578 1579 /* 1580 * I/O macros and structures. 1581 * ------------------------- 1582 */ 1583 1584 /* 1585 * The device's L3 and L4 protocol numbers. These are specific to the 1586 * ENA device and not to be confused with IANA protocol numbers. 1587 * 1588 * common: ena_eth_io_l3_proto_index 1589 */ 1590 typedef enum enahw_io_l3_proto { 1591 ENAHW_IO_L3_PROTO_UNKNOWN = 0, 1592 ENAHW_IO_L3_PROTO_IPV4 = 8, 1593 ENAHW_IO_L3_PROTO_IPV6 = 11, 1594 ENAHW_IO_L3_PROTO_FCOE = 21, 1595 ENAHW_IO_L3_PROTO_ROCE = 22, 1596 } enahw_io_l3_proto_t; 1597 1598 /* common: ena_eth_io_l4_proto_index */ 1599 typedef enum enahw_io_l4_proto { 1600 ENAHW_IO_L4_PROTO_UNKNOWN = 0, 1601 ENAHW_IO_L4_PROTO_TCP = 12, 1602 ENAHW_IO_L4_PROTO_UDP = 13, 1603 ENAHW_IO_L4_PROTO_ROUTEABLE_ROCE = 23, 1604 } enahw_io_l4_proto_t; 1605 1606 /* common: ena_eth_io_tx_desc */ 1607 typedef struct enahw_tx_data_desc { 1608 /* 1609 * 15-0 Buffer Length (LENGTH) 1610 * 1611 * The buffer length in bytes. This should NOT include the 1612 * Ethernet FCS bytes. 1613 * 1614 * 21-16 Request ID High Bits [15-10] (REQ_ID_HI) 1615 * 22 Reserved Zero 1616 * 23 Metadata Flag always zero (META_DESC) 1617 * 1618 * This flag indicates if the descriptor is a metadata 1619 * descriptor or not. In this case we are defining the Tx 1620 * descriptor, so it's always zero. 1621 * 1622 * 24 Phase bit (PHASE) 1623 * 25 Reserved Zero 1624 * 26 First Descriptor Bit (FIRST) 1625 * 1626 * Indicates this is the first descriptor for the frame. 1627 * 1628 * 27 Last Descriptor Bit (LAST) 1629 * 1630 * Indicates this is the last descriptor for the frame. 1631 * 1632 * 28 Completion Request Bit (COMP_REQ) 1633 * 1634 * Indicates if completion should be posted after the 1635 * frame is transmitted. This bit is only valid on the 1636 * first descriptor. 1637 * 1638 * 31-29 Reserved Zero 1639 */ 1640 uint32_t etd_len_ctrl; 1641 1642 /* 1643 * 3-0 L3 Protocol Number (L3_PROTO_IDX) 1644 * 1645 * The L3 protocol type, one of enahw_io_l3_proto_t. This 1646 * field is required when L3_CSUM_EN or TSO_EN is set. 1647 * 1648 * 4 Don't Fragment Bit (DF) 1649 * 1650 * The value of IPv4 DF. This value must copy the value 1651 * found in the packet's IPv4 header. 1652 * 1653 * 6-5 Reserved Zero 1654 * 7 TSO Bit (TSO_EN) 1655 * 1656 * Enable TCP Segment Offload. 1657 * 1658 * 12-8 L4 Protocol Number (L4_PROTO_IDX) 1659 * 1660 * The L4 protocol type, one of enahw_io_l4_proto_t. This 1661 * field is required when L4_CSUM_EN or TSO_EN are 1662 * set. 1663 * 1664 * 13 L3 Checksum Offload (L3_CSUM_EN) 1665 * 1666 * Enable IPv4 header checksum offload. 1667 * 1668 * 14 L4 Checksum Offload (L4_CSUM_EN) 1669 * 1670 * Enable TCP/UDP checksum offload. 1671 * 1672 * 15 Ethernet FCS Disable (ETHERNET_FCS_DIS) 1673 * 1674 * Disable the device's Ethernet Frame Check sequence. 1675 * 1676 * 16 Reserved Zero 1677 * 17 L4 Partial Checksum Present (L4_CSUM_PARTIAL) 1678 * 1679 * When set it indicates the host has already provided 1680 * the pseudo-header checksum. Otherwise, it is up to the 1681 * device to calculate it. 1682 * 1683 * When set and using TSO the host stack must remember 1684 * not to include the TCP segment length in the supplied 1685 * pseudo-header. 1686 * 1687 * The host stack should provide the pseudo-header 1688 * checksum when using IPv6 with Routing Headers. 1689 * 1690 * 21-18 Reserved Zero 1691 * 31-22 Request ID Low [9-0] (REQ_ID_LO) 1692 */ 1693 uint32_t etd_meta_ctrl; 1694 1695 /* The low 32 bits of the buffer address. */ 1696 uint32_t etd_buff_addr_lo; 1697 1698 /* 1699 * address high and header size 1700 * 1701 * 15-0 Buffer Address High [47-32] (ADDR_HI) 1702 * 1703 * The upper 15 bits of the buffer address. 1704 * 1705 * 23-16 Reserved Zero 1706 * 31-24 Header Length (HEADER_LENGTH) 1707 * 1708 * This field has dubious documentation in the 1709 * common/Linux driver code, even contradicting itself in 1710 * the same sentence. Here's what it says, verbatim: 1711 * 1712 * > Header length. For Low Latency Queues, this fields 1713 * > indicates the number of bytes written to the 1714 * > headers' memory. For normal queues, if packet is TCP 1715 * > or UDP, and longer than max_header_size, then this 1716 * > field should be set to the sum of L4 header offset 1717 * > and L4 header size(without options), otherwise, this 1718 * > field should be set to 0. For both modes, this field 1719 * > must not exceed the max_header_size. max_header_size 1720 * > value is reported by the Max Queues Feature 1721 * > descriptor 1722 * 1723 * Here's what one _might_ ascertain from the above. 1724 * 1725 * 1. This field should always be set in the case of 1726 * LLQs/device placement. 1727 * 1728 * 2. This field must _never_ exceed the max header size 1729 * as reported by feature detection. In our code this 1730 * would be efmq_max_header_size for older ENA devices 1731 * and efmqe_max_tx_header_size for newer ones. One 1732 * empirical data point from a t3.small (with newer 1733 * device) is a max Tx header size of 128 bytes. 1734 * 1735 * 3. If the packet is TCP or UDP, and the packet (or the 1736 * headers?) is longer than the max header size, then 1737 * this field should be set to the total header size 1738 * with the exception of TCP header options. 1739 * Otherwise, if the packet is not TCP or UDP, or if 1740 * the packet (or header length?) _does not_ exceed 1741 * the max header size, then set this value to 0. 1742 * 1743 * One might think, based on (3), that when the header 1744 * size exceeds the max this field needs to be set, but 1745 * that contradicts (2), which dictates that the total 1746 * header size can never exceed the max. Sure enough, the 1747 * Linux code drops all packets with headers that exceed 1748 * the max. So in that case it would mean that "and 1749 * longer than max_header_size" is referring to the total 1750 * packet length. So for most workloads, the TCP/UDP 1751 * packets should have this field set, to indicate their 1752 * header length. This matches with Linux, which seems to 1753 * set header length regardless of IP protocol. 1754 * 1755 * However, the FreeBSD code tells a different story. In 1756 * it's non-LLQ Tx path it has the following comment, 1757 * verbatim: 1758 * 1759 * > header_len is just a hint for the device. Because 1760 * > FreeBSD is not giving us information about packet 1761 * > header length and it is not guaranteed that all 1762 * > packet headers will be in the 1st mbuf, setting 1763 * > header_len to 0 is making the device ignore this 1764 * > value and resolve header on it's own. 1765 * 1766 * According to this we can just set the value to zero 1767 * and let the device figure it out. This maps better to 1768 * illumos, where we also allow the header to potentially 1769 * span multiple mblks (though we do have access to the 1770 * header sizes via mac_ether_offload_info_t). 1771 * 1772 * The upshot: for now we take advantage of the device's 1773 * ability to determine the header length on its own, at 1774 * the potential cost of some performance (not measured). 1775 */ 1776 uint32_t etd_buff_addr_hi_hdr_sz; 1777 } enahw_tx_data_desc_t; 1778 1779 #define ENAHW_TX_DESC_LENGTH_MASK GENMASK(15, 0) 1780 #define ENAHW_TX_DESC_REQ_ID_HI_SHIFT 16 1781 #define ENAHW_TX_DESC_REQ_ID_HI_MASK GENMASK(21, 16) 1782 #define ENAHW_TX_DESC_META_DESC_SHIFT 23 1783 #define ENAHW_TX_DESC_META_DESC_MASK BIT(23) 1784 #define ENAHW_TX_DESC_PHASE_SHIFT 24 1785 #define ENAHW_TX_DESC_PHASE_MASK BIT(24) 1786 #define ENAHW_TX_DESC_FIRST_SHIFT 26 1787 #define ENAHW_TX_DESC_FIRST_MASK BIT(26) 1788 #define ENAHW_TX_DESC_LAST_SHIFT 27 1789 #define ENAHW_TX_DESC_LAST_MASK BIT(27) 1790 #define ENAHW_TX_DESC_COMP_REQ_SHIFT 28 1791 #define ENAHW_TX_DESC_COMP_REQ_MASK BIT(28) 1792 #define ENAHW_TX_DESC_L3_PROTO_IDX_MASK GENMASK(3, 0) 1793 #define ENAHW_TX_DESC_DF_SHIFT 4 1794 #define ENAHW_TX_DESC_DF_MASK BIT(4) 1795 #define ENAHW_TX_DESC_TSO_EN_SHIFT 7 1796 #define ENAHW_TX_DESC_TSO_EN_MASK BIT(7) 1797 #define ENAHW_TX_DESC_L4_PROTO_IDX_SHIFT 8 1798 #define ENAHW_TX_DESC_L4_PROTO_IDX_MASK GENMASK(12, 8) 1799 #define ENAHW_TX_DESC_L3_CSUM_EN_SHIFT 13 1800 #define ENAHW_TX_DESC_L3_CSUM_EN_MASK BIT(13) 1801 #define ENAHW_TX_DESC_L4_CSUM_EN_SHIFT 14 1802 #define ENAHW_TX_DESC_L4_CSUM_EN_MASK BIT(14) 1803 #define ENAHW_TX_DESC_ETHERNET_FCS_DIS_SHIFT 15 1804 #define ENAHW_TX_DESC_ETHERNET_FCS_DIS_MASK BIT(15) 1805 #define ENAHW_TX_DESC_L4_CSUM_PARTIAL_SHIFT 17 1806 #define ENAHW_TX_DESC_L4_CSUM_PARTIAL_MASK BIT(17) 1807 #define ENAHW_TX_DESC_REQ_ID_LO_SHIFT 22 1808 #define ENAHW_TX_DESC_REQ_ID_LO_MASK GENMASK(31, 22) 1809 #define ENAHW_TX_DESC_ADDR_HI_MASK GENMASK(15, 0) 1810 #define ENAHW_TX_DESC_HEADER_LENGTH_SHIFT 24 1811 #define ENAHW_TX_DESC_HEADER_LENGTH_MASK GENMASK(31, 24) 1812 1813 #define ENAHW_TX_DESC_LENGTH(desc, len) \ 1814 (((desc)->etd_len_ctrl) |= ((len) & ENAHW_TX_DESC_LENGTH_MASK)) 1815 1816 #define ENAHW_TX_DESC_FIRST_ON(desc) \ 1817 (((desc)->etd_len_ctrl) |= ENAHW_TX_DESC_FIRST_MASK) 1818 1819 #define ENAHW_TX_DESC_FIRST_OFF(desc) \ 1820 (((desc)->etd_len_ctrl) &= ~ENAHW_TX_DESC_FIRST_MASK) 1821 1822 #define ENAHW_TX_DESC_REQID_HI(desc, reqid) \ 1823 (((desc)->etd_len_ctrl) |= \ 1824 ((((reqid) >> 10) << ENAHW_TX_DESC_REQ_ID_HI_SHIFT) & \ 1825 ENAHW_TX_DESC_REQ_ID_HI_MASK)) 1826 1827 #define ENAHW_TX_DESC_REQID_LO(desc, reqid) \ 1828 (((desc)->etd_meta_ctrl) |= \ 1829 (((reqid) << ENAHW_TX_DESC_REQ_ID_LO_SHIFT) & \ 1830 ENAHW_TX_DESC_REQ_ID_LO_MASK)) 1831 1832 #define ENAHW_TX_DESC_PHASE(desc, phase) \ 1833 (((desc)->etd_len_ctrl) |= (((phase) << ENAHW_TX_DESC_PHASE_SHIFT) & \ 1834 ENAHW_TX_DESC_PHASE_MASK)) 1835 1836 #define ENAHW_TX_DESC_LAST_ON(desc) \ 1837 (((desc)->etd_len_ctrl) |= ENAHW_TX_DESC_LAST_MASK) 1838 1839 #define ENAHW_TX_DESC_LAST_OFF(desc) \ 1840 (((desc)->etd_len_ctrl) &= ~ENAHW_TX_DESC_LAST_MASK) 1841 1842 #define ENAHW_TX_DESC_COMP_REQ_ON(desc) \ 1843 (((desc)->etd_len_ctrl) |= ENAHW_TX_DESC_COMP_REQ_MASK) 1844 1845 #define ENAHW_TX_DESC_COMP_REQ_OFF(desc) \ 1846 (((desc)->etd_len_ctrl) &= ~ENAHW_TX_DESC_COMP_REQ_MASK) 1847 1848 #define ENAHW_TX_DESC_META_DESC_ON(desc) \ 1849 (((desc)->etd_len_ctrl) |= ENAHW_TX_DESC_META_DESC_MASK) 1850 1851 #define ENAHW_TX_DESC_META_DESC_OFF(desc) \ 1852 (((desc)->etd_len_ctrl) &= ~ENAHW_TX_DESC_META_DESC_MASK) 1853 1854 #define ENAHW_TX_DESC_ADDR_LO(desc, addr) \ 1855 (((desc)->etd_buff_addr_lo) = (addr)) 1856 1857 #define ENAHW_TX_DESC_ADDR_HI(desc, addr) \ 1858 (((desc)->etd_buff_addr_hi_hdr_sz) |= \ 1859 (((addr) >> 32) & ENAHW_TX_DESC_ADDR_HI_MASK)) 1860 1861 #define ENAHW_TX_DESC_HEADER_LENGTH(desc, len) \ 1862 (((desc)->etd_buff_addr_hi_hdr_sz) |= \ 1863 (((len) << ENAHW_TX_DESC_HEADER_LENGTH_SHIFT) & \ 1864 ENAHW_TX_DESC_HEADER_LENGTH_MASK)) 1865 1866 #define ENAHW_TX_DESC_DF_ON(desc) \ 1867 ((desc)->etd_meta_ctrl |= ENAHW_TX_DESC_DF_MASK) 1868 1869 #define ENAHW_TX_DESC_TSO_OFF(desc) \ 1870 (((desc)->etd_meta_ctrl) &= ~ENAHW_TX_DESC_TSO_EN_MASK) 1871 1872 #define ENAHW_TX_DESC_L3_CSUM_OFF(desc) \ 1873 (((desc)->etd_meta_ctrl) &= ~ENAHW_TX_DESC_L3_CSUM_EN_MASK) 1874 1875 #define ENAHW_TX_DESC_L4_CSUM_OFF(desc) \ 1876 (((desc)->etd_meta_ctrl) &= ~ENAHW_TX_DESC_L4_CSUM_EN_MASK) 1877 1878 #define ENAHW_TX_DESC_L4_CSUM_PARTIAL_ON(desc) \ 1879 (((desc)->etd_meta_ctrl) &= ~ENAHW_TX_DESC_L4_CSUM_PARTIAL_MASK) 1880 1881 /* common: ena_eth_io_tx_meta_desc */ 1882 typedef struct enahw_tx_meta_desc { 1883 /* 1884 * 9-0 Request ID Low [9-0] (REQ_ID_LO) 1885 * 13-10 Reserved Zero 1886 * 14 Extended Metadata Valid (EXT_VALID) 1887 * 1888 * When set this descriptor contains valid extended 1889 * metadata. The extended metadata includes the L3/L4 1890 * length and offset fields as well as the MSS bits. This 1891 * is needed for TSO. 1892 * 1893 * 15 Reserved Zero 1894 * 19-16 MSS High Bits (MSS_HI) 1895 * 20 Meta Type (ETH_META_TYPE) 1896 * 1897 * If enabled this is an extended metadata descriptor. 1898 * This seems redundant with EXT_VALID. 1899 * 1900 * 21 Meta Store (META_STORE) 1901 * 1902 * Store the extended metadata in the queue cache. 1903 * 1904 * 22 Reserved Zero 1905 * 23 Metadata Flag (META_DESC) -- always one 1906 * 24 Phase (PHASE) 1907 * 25 Reserved Zero 1908 * 26 First Descriptor Bit (FIRST) 1909 * 27 Last Descriptor Bit (LAST) 1910 * 28 Completion Request Bit (COMP_REQ) 1911 * 31-29 Reserved Zero 1912 */ 1913 uint32_t etmd_len_ctrl; 1914 1915 /* 1916 * 5-0 Request ID High Bits [15-10] (REQ_ID_HI) 1917 * 31-6 Reserved Zero 1918 */ 1919 uint32_t etmd_word1; 1920 1921 /* 1922 * 7-0 L3 Header Length (L3_HDR_LEN) 1923 * 15:8 L3 Header Offset (L3_HDR_OFF) 1924 * 21:16 L4 Header Length in Words (L4_HDR_LEN_IN_WORDS) 1925 * 1926 * Specifies the L4 header length in words. The device 1927 * assumes the L4 header follows directly after the L3 1928 * header and that the L4 offset is equal to L3_HDR_OFF + 1929 * L3_HDR_LEN. 1930 * 1931 * 31-22 MSS Low Bits (MSS_LO) 1932 */ 1933 uint32_t etmd_word2; 1934 uint32_t etmd_reserved; 1935 } enahw_tx_meta_desc_t; 1936 1937 #define ENAHW_TX_META_DESC_REQ_ID_LO_MASK GENMASK(9, 0) 1938 #define ENAHW_TX_META_DESC_EXT_VALID_SHIFT 14 1939 #define ENAHW_TX_META_DESC_EXT_VALID_MASK BIT(14) 1940 #define ENAHW_TX_META_DESC_MSS_HI_SHIFT 16 1941 #define ENAHW_TX_META_DESC_MSS_HI_MASK GENMASK(19, 16) 1942 #define ENAHW_TX_META_DESC_ETH_META_TYPE_SHIFT 20 1943 #define ENAHW_TX_META_DESC_ETH_META_TYPE_MASK BIT(20) 1944 #define ENAHW_TX_META_DESC_META_STORE_SHIFT 21 1945 #define ENAHW_TX_META_DESC_META_STORE_MASK BIT(21) 1946 /* Bits 23-28 share positions with the data descriptor. */ 1947 #define ENAHW_TX_META_DESC_META_DESC_MASK BIT(23) 1948 #define ENAHW_TX_META_DESC_PHASE_SHIFT 24 1949 #define ENAHW_TX_META_DESC_PHASE_MASK BIT(24) 1950 #define ENAHW_TX_META_DESC_FIRST_MASK BIT(26) 1951 #define ENAHW_TX_META_DESC_LAST_MASK BIT(27) 1952 #define ENAHW_TX_META_DESC_COMP_REQ_MASK BIT(28) 1953 #define ENAHW_TX_META_DESC_REQ_ID_HI_MASK GENMASK(5, 0) 1954 1955 #define ENAHW_TX_META_DESC_L3_HDR_LEN_MASK GENMASK(7, 0) 1956 #define ENAHW_TX_META_DESC_L3_HDR_OFF_SHIFT 8 1957 #define ENAHW_TX_META_DESC_L3_HDR_OFF_MASK GENMASK(15, 8) 1958 #define ENAHW_TX_META_DESC_L4_HDR_LEN_SHIFT 16 1959 #define ENAHW_TX_META_DESC_L4_HDR_LEN_MASK GENMASK(21, 16) 1960 #define ENAHW_TX_META_DESC_MSS_LO_SHIFT 22 1961 #define ENAHW_TX_META_DESC_MSS_LO_MASK GENMASK(31, 22) 1962 1963 #define ENAHW_TX_META_DESC_META_DESC_ON(desc) \ 1964 ((desc)->etmd_len_ctrl |= ENAHW_TX_META_DESC_META_DESC_MASK) 1965 1966 #define ENAHW_TX_META_DESC_EXT_VALID_ON(desc) \ 1967 ((desc)->etmd_len_ctrl |= ENAHW_TX_META_DESC_EXT_VALID_MASK) 1968 1969 #define ENAHW_TX_META_DESC_ETH_META_TYPE_ON(desc) \ 1970 ((desc)->etmd_len_ctrl |= ENAHW_TX_META_DESC_ETH_META_TYPE_MASK) 1971 1972 #define ENAHW_TX_META_DESC_META_STORE_ON(desc) \ 1973 ((desc)->etmd_len_ctrl |= ENAHW_TX_META_DESC_META_STORE_MASK) 1974 1975 #define ENAHW_TX_META_DESC_PHASE(desc, phase) \ 1976 ((desc)->etmd_len_ctrl |= \ 1977 (((phase) << ENAHW_TX_META_DESC_PHASE_SHIFT) & \ 1978 ENAHW_TX_META_DESC_PHASE_MASK)) 1979 1980 #define ENAHW_TX_META_DESC_FIRST_ON(desc) \ 1981 ((desc)->etmd_len_ctrl |= ENAHW_TX_META_DESC_FIRST_MASK) 1982 1983 #define ENAHW_TX_META_DESC_COMP_REQ_ON(desc) \ 1984 ((desc)->etmd_len_ctrl |= ENAHW_TX_META_DESC_COMP_REQ_MASK) 1985 1986 #define ENAHW_TX_META_DESC_L3_HDR_OFF(desc, off) \ 1987 ((desc)->etmd_word2 |= \ 1988 (((off) << ENAHW_TX_META_DESC_L3_HDR_OFF_SHIFT) & \ 1989 ENAHW_TX_META_DESC_L3_HDR_OFF_MASK)) 1990 1991 /* common: N/A */ 1992 typedef union enahw_tx_desc { 1993 enahw_tx_data_desc_t etd_data; 1994 enahw_tx_meta_desc_t etd_meta; 1995 } enahw_tx_desc_t; 1996 1997 /* common: ena_eth_io_tx_cdesc */ 1998 typedef struct enahw_tx_cdesc { 1999 /* 2000 * 15-0 Request ID Bits 2001 * 16 Reserved Zero 2002 */ 2003 uint16_t etc_req_id; 2004 2005 /* 2006 * Presumably the status of the Tx, though the Linux driver 2007 * never checks this field. 2008 */ 2009 uint8_t etc_status; 2010 2011 /* 2012 * 0 Phase 2013 * 7-1 Reserved Zero 2014 */ 2015 uint8_t etc_flags; 2016 2017 /* 2018 * This isn't documented or used in the Linux driver, but 2019 * these probably store the submission queue ID and the 2020 * submission queue head index. 2021 */ 2022 uint16_t etc_sub_qid; 2023 uint16_t etc_sq_head_idx; 2024 } enahw_tx_cdesc_t; 2025 2026 #define ENAHW_TX_CDESC_PHASE_SHIFT 0 2027 #define ENAHW_TX_CDESC_PHASE_MASK BIT(0) 2028 2029 #define ENAHW_TX_CDESC_GET_PHASE(cdesc) \ 2030 ((cdesc)->etc_flags & ENAHW_TX_CDESC_PHASE_MASK) 2031 2032 /* common: ena_eth_io_rx_desc */ 2033 typedef struct enahw_rx_desc { 2034 /* 2035 * The length of the buffer provided by the host, in bytes. 2036 * Use the value of 0 to indicate 64K. 2037 */ 2038 uint16_t erd_length; 2039 uint8_t erd_reserved1; 2040 2041 /* 2042 * 0 Phase (PHASE) 2043 * 1 Reserved Zero 2044 * 2 First (FIRST) 2045 * 2046 * Indicates this is the first descriptor for the frame. 2047 * 2048 * 3 Last (LAST) 2049 * 2050 * Indicates this is the last descriptor for the frame. 2051 * 2052 * 4 Completion Request (COMP_REQ) 2053 * 2054 * Indicates that a completion request should be generated 2055 * for this descriptor. 2056 * 2057 * 7-5 Reserved Zero 2058 */ 2059 uint8_t erd_ctrl; 2060 2061 /* 2062 * 15-0 Request ID 2063 * 16 Reserved 0 2064 */ 2065 uint16_t erd_req_id; 2066 uint16_t erd_reserved2; 2067 2068 /* The physical address of the buffer provided by the host. */ 2069 uint32_t erd_buff_addr_lo; 2070 uint16_t erd_buff_addr_hi; 2071 uint16_t erd_reserved3; 2072 } enahw_rx_desc_t; 2073 2074 #define ENAHW_RX_DESC_PHASE_MASK BIT(0) 2075 #define ENAHW_RX_DESC_FIRST_SHIFT 2 2076 #define ENAHW_RX_DESC_FIRST_MASK BIT(2) 2077 #define ENAHW_RX_DESC_LAST_SHIFT 3 2078 #define ENAHW_RX_DESC_LAST_MASK BIT(3) 2079 #define ENAHW_RX_DESC_COMP_REQ_SHIFT 4 2080 #define ENAHW_RX_DESC_COMP_REQ_MASK BIT(4) 2081 2082 #define ENAHW_RX_DESC_CLEAR_CTRL(desc) ((desc)->erd_ctrl = 0) 2083 #define ENAHW_RX_DESC_SET_PHASE(desc, val) \ 2084 ((desc)->erd_ctrl |= ((val) & ENAHW_RX_DESC_PHASE_MASK)) 2085 2086 #define ENAHW_RX_DESC_SET_FIRST(desc) \ 2087 ((desc)->erd_ctrl |= ENAHW_RX_DESC_FIRST_MASK) 2088 2089 #define ENAHW_RX_DESC_SET_LAST(desc) \ 2090 ((desc)->erd_ctrl |= ENAHW_RX_DESC_LAST_MASK) 2091 2092 #define ENAHW_RX_DESC_SET_COMP_REQ(desc) \ 2093 ((desc)->erd_ctrl |= ENAHW_RX_DESC_COMP_REQ_MASK) 2094 2095 /* 2096 * Ethernet parsing information is only valid when last == 1. 2097 * 2098 * common: ena_eth_io_rx_cdesc_base 2099 */ 2100 typedef struct enahw_rx_cdesc { 2101 /* 2102 * 4-0 L3 Protocol Number (L3_PROTO) 2103 * 2104 * The L3 protocol type, one of enahw_io_l3_proto_t. 2105 * 2106 * 6-5 (SRC_VLAN_CNT) 2107 * 7 Reserved Zero 2108 * 12-8 L4 Protocol Number (L4_PROTO) 2109 * 13 L3 Checksum Error (L3_CSUM_ERR) 2110 * 2111 * When set either the L3 checksum failed to match or the 2112 * controller didn't attempt to validate the checksum. 2113 * This bit is valid only when L3_PROTO indicates an IPv4 2114 * packet. 2115 * 2116 * 14 L4 Checksum Error (L4_CSUM_ERR) 2117 * 2118 * When set either the L4 checksum failed to match or the 2119 * controller didn't attempt to validate the checksum. 2120 * This bit is valid only when L4_PROTO indicates a 2121 * TCP/UDP packet, IPV4_FRAG is not set, and 2122 * L4_CSUM_CHECKED is set. 2123 * 2124 * 15 IPv4 Fragmented (IPV4_FRAG) 2125 * 16 L4 Checksum Validated (L4_CSUM_CHECKED) 2126 * 2127 * When set it indicates the device attempted to validate 2128 * the L4 checksum. 2129 * 2130 * 23-17 Reserved Zero 2131 * 24 Phase (PHASE) 2132 * 25 (L3_CSUM2) 2133 * 2134 * According to the Linux source this is the "second 2135 * checksum engine result". It's never checked. 2136 * 2137 * 26 First Descriptor Bit (FIRST) 2138 * 2139 * Indicates the first descriptor for the frame. 2140 * 2141 * 27 Last Descriptor Bit (LAST) 2142 * 2143 * Indicates the last descriptor for the frame. 2144 * 2145 * 29-28 Reserved Zero 2146 * 30 Buffer Type (BUFFER) 2147 * 2148 * When enabled indicates this is a data descriptor. 2149 * Otherwse, it is a metadata descriptor. 2150 * 2151 * 31 : reserved31 2152 */ 2153 uint32_t erc_status; 2154 uint16_t erc_length; 2155 uint16_t erc_req_id; 2156 2157 /* 32-bit hash result */ 2158 uint32_t erc_hash; 2159 uint16_t erc_sub_qid; 2160 2161 /* 2162 * The device may choose to offset the start of the header 2163 * data (which implies this value only applies to the first 2164 * descriptor). When and why the device does this is not 2165 * documented in the common code. The most likely case would 2166 * be for IP header alignment. 2167 */ 2168 uint8_t erc_offset; 2169 uint8_t erc_reserved; 2170 } enahw_rx_cdesc_t; 2171 2172 #define ENAHW_RX_CDESC_L3_PROTO_MASK GENMASK(4, 0) 2173 #define ENAHW_RX_CDESC_SRC_VLAN_CNT_SHIFT 5 2174 #define ENAHW_RX_CDESC_SRC_VLAN_CNT_MASK GENMASK(6, 5) 2175 #define ENAHW_RX_CDESC_L4_PROTO_SHIFT 8 2176 #define ENAHW_RX_CDESC_L4_PROTO_MASK GENMASK(12, 8) 2177 #define ENAHW_RX_CDESC_L3_CSUM_ERR_SHIFT 13 2178 #define ENAHW_RX_CDESC_L3_CSUM_ERR_MASK BIT(13) 2179 #define ENAHW_RX_CDESC_L4_CSUM_ERR_SHIFT 14 2180 #define ENAHW_RX_CDESC_L4_CSUM_ERR_MASK BIT(14) 2181 #define ENAHW_RX_CDESC_IPV4_FRAG_SHIFT 15 2182 #define ENAHW_RX_CDESC_IPV4_FRAG_MASK BIT(15) 2183 #define ENAHW_RX_CDESC_L4_CSUM_CHECKED_SHIFT 16 2184 #define ENAHW_RX_CDESC_L4_CSUM_CHECKED_MASK BIT(16) 2185 #define ENAHW_RX_CDESC_PHASE_SHIFT 24 2186 #define ENAHW_RX_CDESC_PHASE_MASK BIT(24) 2187 #define ENAHW_RX_CDESC_L3_CSUM2_SHIFT 25 2188 #define ENAHW_RX_CDESC_L3_CSUM2_MASK BIT(25) 2189 #define ENAHW_RX_CDESC_FIRST_SHIFT 26 2190 #define ENAHW_RX_CDESC_FIRST_MASK BIT(26) 2191 #define ENAHW_RX_CDESC_LAST_SHIFT 27 2192 #define ENAHW_RX_CDESC_LAST_MASK BIT(27) 2193 #define ENAHW_RX_CDESC_BUFFER_SHIFT 30 2194 #define ENAHW_RX_CDESC_BUFFER_MASK BIT(30) 2195 2196 #define ENAHW_RX_CDESC_L3_PROTO(desc) \ 2197 ((desc)->erc_status & ENAHW_RX_CDESC_L3_PROTO_MASK) 2198 2199 #define ENAHW_RX_CDESC_L3_CSUM_ERR(desc) \ 2200 ((((desc)->erc_status & ENAHW_RX_CDESC_L3_CSUM_ERR_MASK) >> \ 2201 ENAHW_RX_CDESC_L3_CSUM_ERR_SHIFT) != 0) 2202 2203 #define ENAHW_RX_CDESC_L4_PROTO(desc) \ 2204 (((desc)->erc_status & ENAHW_RX_CDESC_L4_PROTO_MASK) >> \ 2205 ENAHW_RX_CDESC_L4_PROTO_SHIFT) 2206 2207 #define ENAHW_RX_CDESC_L4_CSUM_CHECKED(desc) \ 2208 ((((desc)->erc_status & ENAHW_RX_CDESC_L4_CSUM_CHECKED_MASK) >> \ 2209 ENAHW_RX_CDESC_L4_CSUM_CHECKED_SHIFT) != 0) 2210 2211 #define ENAHW_RX_CDESC_L4_CSUM_ERR(desc) \ 2212 ((((desc)->erc_status & ENAHW_RX_CDESC_L4_CSUM_ERR_MASK) >> \ 2213 ENAHW_RX_CDESC_L4_CSUM_ERR_SHIFT) != 0) 2214 2215 #define ENAHW_RX_CDESC_PHASE(desc) \ 2216 (((desc)->erc_status & ENAHW_RX_CDESC_PHASE_MASK) >> \ 2217 ENAHW_RX_CDESC_PHASE_SHIFT) 2218 2219 #define ENAHW_RX_CDESC_FIRST(desc) \ 2220 ((((desc)->erc_status & ENAHW_RX_CDESC_FIRST_MASK) >> \ 2221 ENAHW_RX_CDESC_FIRST_SHIFT) == 1) 2222 2223 #define ENAHW_RX_CDESC_LAST(desc) \ 2224 ((((desc)->erc_status & ENAHW_RX_CDESC_LAST_MASK) >> \ 2225 ENAHW_RX_CDESC_LAST_SHIFT) == 1) 2226 2227 /* 2228 * Controls for the interrupt register mapped to each Rx/Tx CQ. 2229 */ 2230 #define ENAHW_REG_INTR_RX_DELAY_MASK GENMASK(14, 0) 2231 #define ENAHW_REG_INTR_TX_DELAY_SHIFT 15 2232 #define ENAHW_REG_INTR_TX_DELAY_MASK GENMASK(29, 15) 2233 #define ENAHW_REG_INTR_UNMASK_SHIFT 30 2234 #define ENAHW_REG_INTR_UNMASK_MASK BIT(30) 2235 2236 #define ENAHW_REG_INTR_UNMASK(val) \ 2237 ((val) |= ENAHW_REG_INTR_UNMASK_MASK) 2238 2239 #define ENAHW_REG_INTR_MASK(val) \ 2240 ((val) &= ~ENAHW_REG_INTR_UNMASK_MASK) 2241 2242 #endif /* _ENA_HW_H */ 2243