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Searched refs:ctl_reg (Results 1 – 3 of 3) sorted by relevance

/illumos-gate/usr/src/uts/intel/io/vmm/intel/
H A Dvmx_msr.c75 vmx_set_ctlreg(int ctl_reg, int true_ctl_reg, uint32_t ones_mask, in vmx_set_ctlreg() argument
88 val = rdmsr(ctl_reg); in vmx_set_ctlreg()
100 "truectl 0x%0x\n", i, ctl_reg, true_ctl_reg)); in vmx_set_ctlreg()
129 "0x%0x and true msr 0x%0x", i, ctl_reg, in vmx_set_ctlreg()
H A Dvmx_msr.h42 int vmx_set_ctlreg(int ctl_reg, int true_ctl_reg, uint32_t ones_mask,
/illumos-gate/usr/src/uts/common/io/cxgbe/common/
H A Dt4_hw.c351 u32 ctl_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_CTRL); in t4_wr_mbox_meat_timeout() local
418 ctl = t4_read_reg(adap, ctl_reg); in t4_wr_mbox_meat_timeout()
469 t4_write_reg(adap, ctl_reg, F_MBMSGVALID | V_MBOWNER(X_MBOWNER_FW)); in t4_wr_mbox_meat_timeout()
470 (void) t4_read_reg(adap, ctl_reg); /* flush write */ in t4_wr_mbox_meat_timeout()
487 v = t4_read_reg(adap, ctl_reg); in t4_wr_mbox_meat_timeout()
492 t4_write_reg(adap, ctl_reg, in t4_wr_mbox_meat_timeout()
501 t4_write_reg(adap, ctl_reg, V_MBOWNER(X_MBOWNER_NONE)); in t4_wr_mbox_meat_timeout()
572 u32 ctl_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_CTRL); in t4_wr_mbox_meat_timeout_panic() local
595 ctl = t4_read_reg(adap, ctl_reg); in t4_wr_mbox_meat_timeout_panic()
638 t4_write_reg(adap, ctl_reg, F_MBMSGVALID | V_MBOWNER(X_MBOWNER_FW)); in t4_wr_mbox_meat_timeout_panic()
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