1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * Copyright 2024 Oxide Computer Company 14 */ 15 16 #ifndef _SPD_LP4_H 17 #define _SPD_LP4_H 18 19 /* 20 * Definitions for use in LPDDR3, LPDDR4, and LPDDR4x Serial Presence Decoding 21 * based on JEDEC Standard 21-C Section Title: Annex M: Serial Presence Detect 22 * (SPD) for LPDDR3 and LPDDR4 SDRAM Modules Release 2. While this covers 23 * multiple revisions, we'll generally refer to this collectively as LPDDR4. 24 * 25 * LPDDR4 modules are organized into a few regions that are generally similar to 26 * DDR4, though the contents vary: 27 * 28 * o Base Configuration and DRAM parameters (bytes 0x00-0x7f) 29 * o Standard Module Parameters (bytes 0x80-0xff) these vary on whether 30 * something is an LP-DIMM or soldered down. 31 * o Hybrid Module Extended Parameters (bytes 0x100-0x13f). 32 * o Manufacturing Information (bytes 0x140-0x17f) 33 * o End User Programmable data (0x180-0x1ff). 34 */ 35 36 #include <sys/bitext.h> 37 #include "spd_common.h" 38 39 #ifdef __cplusplus 40 extern "C" { 41 #endif 42 43 /* 44 * S3.1.1 Number of Bytes Used / Number of Bytes in SPD Device. 45 */ 46 #define SPD_LP4_NBYTES 0x000 47 #define SPD_LP4_NBYTES_TOTAL(r) bitx8(r, 6, 4) 48 #define SPD_LP4_NBYTES_TOTAL_UNDEF 0 49 #define SPD_LP4_NBYTES_TOTAL_256 1 50 #define SPD_LP4_NBYTES_TOTAL_512 2 51 #define SPD_LP4_NBYTES_USED(r) bitx8(r, 3, 0) 52 #define SPD_LP4_NBYTES_USED_UNDEF 0 53 #define SPD_LP4_NBYTES_USED_128 1 54 #define SPD_LP4_NBYTES_USED_256 2 55 #define SPD_LP4_NBYTES_USED_384 3 56 #define SPD_LP4_NBYTES_USED_512 4 57 58 59 /* 60 * S3.1.2 SPD Revision. This is the same as described in SPD_DDR4_SPD_REV as 61 * defined in spd_ddr4.h. 62 */ 63 #define SPD_LP4_SPD_REV 0x001 64 #define SPD_LP4_SPD_REV_ENC(r) bitx8(r, 7, 4) 65 #define SPD_LP4_SPD_REV_ADD(r) bitx8(r, 3, 0) 66 #define SPD_LP4_SPD_REV_V1 1 67 68 /* 69 * Key Byte / DRAM Device Type. This field identifies the type of DDR device and 70 * is actually consistent across all SPD versions. Known values are in the 71 * spd_dram_type_t enumeration. 72 */ 73 #define SPD_LP4_DRAM_TYPE 0x002 74 75 /* 76 * S3.1.4: Key Byte / Module type. This is used to describe what kind of DDR 77 * module it is, which tell us what the module-specific section contents are. 78 * These bits, unlike the one above are device specific. 79 */ 80 #define SPD_LP4_MOD_TYPE 0x003 81 #define SPD_LP4_MOD_TYPE_ISHYBRID(r) bitx8(r, 7, 7) 82 #define SPD_LP4_MOD_TYPE_HYBRID(r) bitx8(r, 6, 4) 83 #define SPD_LP4_MOD_TYPE_HYBRID_NONE 0 84 #define SPD_LP4_MOD_TYPE_TYPE(r) bitx8(r, 3, 0) 85 #define SPD_LP4_MOD_TYPE_TYPE_EXT 0 86 #define SPD_LP4_MOD_TYPE_TYPE_LPDIMM 0x7 87 #define SPD_LP4_MOD_TYPE_TYPE_SOLDER 0xe 88 89 /* 90 * S3.1.5 SDRAM Density and Banks. 91 */ 92 #define SPD_LP4_DENSITY 0x004 93 #define SPD_LP4_DENSITY_NBG_BITS(r) bitx8(r, 7, 6) 94 #define SPD_LP4_DENSITY_NBG_BITS_MAX 2 95 #define SPD_LP4_DENSITY_NBA_BITS(r) bitx8(r, 5, 4) 96 #define SPD_LP4_DENSITY_NBA_BITS_BASE 2 97 #define SPD_LP4_DENSITY_NBA_BITS_MAX 3 98 #define SPD_LP4_DENSITY_DENSITY(r) bitx8(r, 3, 0) 99 #define SPD_LP4_DENSITY_DENSITY_1Gb 2 100 #define SPD_LP4_DENSITY_DENSITY_2Gb 3 101 #define SPD_LP4_DENSITY_DENSITY_4Gb 4 102 #define SPD_LP4_DENSITY_DENSITY_8Gb 5 103 #define SPD_LP4_DENSITY_DENSITY_16Gb 6 104 #define SPD_LP4_DENSITY_DENSITY_32Gb 7 105 #define SPD_LP4_DENSITY_DENSITY_12Gb 8 106 #define SPD_LP4_DENSITY_DENSITY_24Gb 9 107 #define SPD_LP4_DENSITY_DENSITY_3Gb 10 108 #define SPD_LP4_DENSITY_DENSITY_6Gb 11 109 #define SPD_LP4_DENSITY_DENSITY_18Gb 12 110 111 /* 112 * S3.1.6 SDRAM Addressing. 113 */ 114 #define SPD_LP4_ADDR 0x005 115 #define SPD_LP4_ADDR_NROWS(r) bitx8(r, 5, 3) 116 #define SPD_LP4_ADDR_NROWS_BASE 12 117 #define SPD_LP4_ADDR_NROWS_MAX 18 118 #define SPD_LP4_ADDR_NCOLS(r) bitx8(r, 2, 0) 119 #define SPD_LP4_ADDR_NCOLS_BASE 9 120 #define SPD_LP4_ADDR_NCOLS_MAX 12 121 122 /* 123 * S3.1.7 SDRAM Package Type 124 */ 125 #define SPD_LP4_PKG 0x006 126 #define SPD_LP4_PKG_TYPE(r) bitx8(r, 7, 7) 127 #define SPD_LP4_PKG_TYPE_MONO 0 128 #define SPD_LP4_PKG_TYPE_NOT 1 129 #define SPD_LP4_PKG_DIE_CNT(r) bitx8(r, 6, 4) 130 #define SPD_LP4_PKG_DIE_CNT_BASE 1 131 #define SPD_LP4_PKG_NCHAN(r) bitx8(r, 3, 2) 132 #define SPD_LP4_PKG_NCHAN_MAX 4 133 #define SPD_LP4_PKG_SL(r) bitx8(r, 1, 0) 134 #define SPD_LP4_PKG_SL_M1 1 135 #define SPD_LP4_PKG_SL_M2 3 136 137 /* 138 * S3.1.8 SDRAM Optional Features. 139 */ 140 #define SPD_LP4_OPT_FEAT 0x007 141 #define SPD_LP4_OPT_FEAT_MAW(r) bitx8(r, 5, 4) 142 #define SPD_LP4_OPT_FEAT_MAW_8192X 0 143 #define SPD_LP4_OPT_FEAT_MAW_4096X 1 144 #define SPD_LP4_OPT_FEAT_MAW_2048X 2 145 #define SPD_LP4_OPT_FEAT_MAC(r) bitx8(r, 3, 0) 146 #define SPD_LP4_OPT_FEAT_MAC_UNTESTED 0 147 #define SPD_LP4_OPT_FEAT_MAC_700K 1 148 #define SPD_LP4_OPT_FEAT_MAC_600K 2 149 #define SPD_LP4_OPT_FEAT_MAC_500K 3 150 #define SPD_LP4_OPT_FEAT_MAC_400K 4 151 #define SPD_LP4_OPT_FEAT_MAC_300K 5 152 #define SPD_LP4_OPT_FEAT_MAC_200K 6 153 #define SPD_LP4_OPT_FEAT_MAC_UNLIMITED 8 154 155 /* 156 * S3.1.10 Other SDRAM Optional Features. These are even more that aren't in the 157 * first set of optional features. 158 */ 159 #define SPD_LP4_OPT_FEAT2 0x009 160 #define SPD_LP4_OPT_FEAT2_PPR(r) bitx8(r, 7, 6) 161 #define SPD_LP4_OPT_FEAT2_PPR_NOTSUP 0 162 #define SPD_LP4_OPT_FEAT2_PPR_1RPBG 1 163 #define SPD_LP4_OPT_FEAT2_SOFT_PPR(r) bitx8(r, 5, 5) 164 165 /* 166 * S3.1.13 Module Organization 167 */ 168 #define SPD_LP4_MOD_ORG 0x00c 169 #define SPD_LP4_MOD_ORG_IDENT(r) bitx8(r, 6, 6) 170 #define SPD_LP4_MOD_ORG_IDENT_STD 0 171 #define SPD_LP4_MOD_ORG_IDENT_BYTE 1 172 #define SPD_LP4_MOD_ORG_RANK_MIX(r) bitx8(r, 6, 6) 173 #define SPD_LP4_MOD_ORG_RANK_MIX_SYM 0 174 #define SPD_LP4_MOD_ORG_RANK_MIX_ASYM 1 175 #define SPD_LP4_MOD_ORG_NPKG_RANK(r) bitx8(r, 5, 3) 176 #define SPD_LP4_MOD_ORG_NPKG_RANK_BASE 1 177 #define SPD_LP4_MOD_ORG_NPKG_RANK_MAX 4 178 #define SPD_LP4_MOD_ORG_WIDTH(r) bitx8(r, 2, 0) 179 #define SPD_LP4_MOD_ORG_WIDTH_BASE 2 180 #define SPD_LP4_MOD_ORG_WIDTH_MAX 32 181 182 /* 183 * S3.1.14 Memory Bus Width. 184 */ 185 #define SPD_LP4_BUS_WIDTH 0x00d 186 #define SPD_LP4_BUS_WIDTH_NCHAN(r) bitx8(r, 7, 5) 187 #define SPD_LP4_BUS_WIDTH_NCHAN_1ch 0 188 #define SPD_LP4_BUS_WIDTH_NCHAN_2ch 1 189 #define SPD_LP4_BUS_WIDTH_NCHAN_3ch 2 190 #define SPD_LP4_BUS_WIDTH_NCHAN_4ch 3 191 #define SPD_LP4_BUS_WIDTH_NCHAN_8ch 4 192 #define SPD_LP4_BUS_WIDTH_EXT(r) bitx8(r, 4, 3) 193 #define SPD_LP4_BUS_WIDTH_EXT_NONE 0 194 #define SPD_LP4_BUS_WIDTH_PRI(r) bitx8(r, 2, 0) 195 #define SPD_LP4_BUS_WIDTH_PRI_BASE 3 196 #define SPD_LP4_BUS_WIDTH_PRI_MAX 64 197 198 /* 199 * S8.1.15 Module Thermal Sensor. 200 */ 201 #define SPD_LP4_MOD_THERM 0x00e 202 #define SPD_LP4_MOD_THERM_PRES(r) bitx8(r, 7, 7) 203 204 /* 205 * S3.1.17 Signal Loading 206 * 207 * The values of the signal loading are dependent on the value found in the 208 * SPD_LP4_PKG (byte 6) register, The interpretation varies based on the value 209 * of SPD_LP4_PKG_SL(). However, the only defined signal loading matrix is 210 * matrix 1. 211 */ 212 #define SPD_LP4_SIGLOAD 0x010 213 #define SPD_LP4_SIGLOAD1_DSM_LOAD(r) bitx8(r, 7, 6) 214 #define SPD_LP4_SIGLOAD1_DSM_LOAD_MAX 4 215 #define SPD_LP4_SIGLOAD1_CAC_LOAD(r) bitx8(r, 5, 3) 216 #define SPD_LP4_SIGLOAD1_CAC_LOAD_MAX 8 217 #define SPD_LP4_SIGLOAD1_CS_LOAD(r) bitx8(r, 2, 0) 218 #define SPD_LP4_SIGLOAD1_CS_LOAD_MAX 8 219 220 /* 221 * Timebases 222 * 223 * Like with DDR4, there are strictly speaking timebase values encoded in the 224 * registers that describe how to calculate other values. These are broken into 225 * the Medium and Fine timebases respectively which as of v1.0 have fixed 226 * values of 125ps and 1ps respectively. See the DDR4 version for more 227 * information. 228 */ 229 #define SPD_LP4_TIMEBASE 0x011 230 #define SPD_LP4_TIMEBASE_MTB(r) bitx8(r, 3, 2) 231 #define SPD_LP4_TIMEBASE_MTB_125ps 0 232 #define SPD_LP4_TIMEBASE_FTB(r) bitx8(r, 1, 0) 233 #define SPD_LP4_TIMEBASE_FTB_1ps 0 234 #define SPD_LP4_MTB_PS 125 235 #define SPD_LP4_FTB_PS 1 236 237 /* 238 * S3.1.19 SDRAM Minimum Cycle Time t~ckavg~min. 239 * S3.1.37 Fine Offset for ^ 240 * S3.1.20 SDRAM Maximum Cycle Time t~ckavg~max. 241 * S3.1.36 Fine Offset for ^ 242 */ 243 #define SPD_LP4_TCKAVG_MIN 0x012 244 #define SPD_LP4_TCKAVG_MIN_FINE 0x07d 245 #define SPD_LP4_TCKAVG_MAX 0x013 246 #define SPD_LP4_TCKAVG_MAX_FINE 0x07c 247 248 /* 249 * S3.1.21 CAS Latencies. These are four bytes that are used to get at what 250 * speeds are supported. These always start at CL3, but the mapping of bits to 251 * CL values is not uniform. 252 */ 253 #define SPD_LP4_CAS_SUP0 0x014 254 #define SPD_LP4_CAS_SUP1 0x015 255 #define SPD_LP4_CAS_SUP2 0x016 256 #define SPD_LP4_CAS_SUP3 0x017 257 258 /* 259 * S3.1.22 Minimum CAS Latency Time t~AA~min. This uses the MTB. 260 * S3.1.35 Fine Offset for ^ 261 */ 262 #define SPD_LP4_TAA_MIN 0x018 263 #define SPD_LP4_TAA_MIN_FINE 0x07b 264 265 /* 266 * S3.1.23 Read and Write Latency Set Options 267 */ 268 #define SPD_LP4_RWLAT 0x019 269 #define SPD_LP4_RWLAT_WRITE(r) bitx8(r, 3, 2) 270 #define SPD_LP4_RWLAT_WRITE_A 0 271 #define SPD_LP4_RWLAT_WRITE_B 1 272 #define SPD_LP4_RWLAT_READ(r) bitx8(r, 1, 0) 273 #define SPD_LP4_RWLAT_DBIRD_DIS 0 274 #define SPD_LP4_RWLAT_DBIRD_EN 1 275 276 /* 277 * S3.1.24 Minimum RAS to CAS Delay Time t~RCD~min. 278 * S3.1.34 Fine Offset for ^ 279 */ 280 #define SPD_LP4_TRCD_MIN 0x01a 281 #define SPD_LP4_TRCD_MIN_FINE 0x07a 282 283 /* 284 * S3.1.25 All Banks Minimum Row Precharge Delay Time t~RPab~min. 285 * S3.1.33 Fine Offset for ^ 286 */ 287 #define SPD_LP4_TRPAB_MIN 0x01b 288 #define SPD_LP4_TRPAB_MIN_FINE 0x079 289 290 /* 291 * S3.1.26 Per Bank Minimum Row Precharge Delay Time t~RPpb~min. 292 * S3.1.32 Fine Offset for ^ 293 */ 294 #define SPD_LP4_TRPPB_MIN 0x01c 295 #define SPD_LP4_TRPPB_MIN_FINE 0x078 296 297 /* 298 * S3.1.27 All Banks Minimum Refresh Recovery Delay Time t~RFCab~min. This is a 299 * 16-bit quantity that is split between a lower and upper value. Both registers 300 * are in terms of the medium time base. 301 */ 302 #define SPD_LP4_TRFCAB_MIN_LO 0x1d 303 #define SPD_LP4_TRFCAB_MIN_HI 0x1e 304 305 /* 306 * S3.1.28 Per Bank Minimum Refresh Recovery Delay Time t~RFCpb~min. This is a 307 * 16-bit quantity that is split between a lower and upper value. Both registers 308 * are in terms of the medium time base. 309 */ 310 #define SPD_LP4_TRFCPB_MIN_LO 0x1f 311 #define SPD_LP4_TRFCPB_MIN_HI 0x20 312 313 /* 314 * S3.1.30 Connector to SDRAM bit mapping. Each of the bytes defines a different 315 * set of pins here. These all have a fairly standard set of transformations 316 * that can be applied. These include a package rank map which only has a single 317 * identity transformation applied and a separate nibble map encoding. 318 */ 319 #define SPD_LP4_MAP_DQ0 0x03c 320 #define SPD_LP4_MAP_DQ4 0x03d 321 #define SPD_LP4_MAP_DQ8 0x03e 322 #define SPD_LP4_MAP_DQ12 0x03f 323 #define SPD_LP4_MAP_DQ16 0x040 324 #define SPD_LP4_MAP_DQ20 0x041 325 #define SPD_LP4_MAP_DQ24 0x042 326 #define SPD_LP4_MAP_DQ28 0x043 327 #define SPD_LP4_MAP_CB0 0x044 328 #define SPD_LP4_MAP_CB4 0x045 329 #define SPD_LP4_MAP_DQ32 0x046 330 #define SPD_LP4_MAP_DQ36 0x047 331 #define SPD_LP4_MAP_DQ40 0x048 332 #define SPD_LP4_MAP_DQ44 0x049 333 #define SPD_LP4_MAP_DQ48 0x04a 334 #define SPD_LP4_MAP_DQ52 0x04b 335 #define SPD_LP4_MAP_DQ56 0x04c 336 #define SPD_LP4_MAP_DQ60 0x04d 337 #define SPD_LP4_MAP_PKG(r) bitx8(r, 7, 6) 338 #define SPD_LP4_MAP_PKG_FLIP 0 339 #define SPD_LP4_MAP_NIBBLE(r) bitx8(r, 5, 5) 340 #define SPD_LP4_MAP_IDX(r) bitx8(r, 4, 0) 341 #define SPD_LP4_MAP_IDX_UNSPEC 0 342 343 /* 344 * S3.1.38 CRC For Base Configuration Section. This is a CRC that covers bytes 345 * 0x00 to 0x7D using a specific CRC16. 346 */ 347 #define SPD_LP4_CRC_LSB 0x07e 348 #define SPD_LP4_CRC_MSB 0x07f 349 350 /* 351 * The manufacturing information section is identical to DDR4. 352 */ 353 354 /* 355 * LPDDR3/4 only define an annex for the LP-DIMM form factor. 356 */ 357 358 /* 359 * S4.1.1 LP-DIMM: Raw Card Extension, Module Nominal Height. Bits 7-5 here have 360 * a raw card revision. The revision extension, bits 7:5, are only valid when 361 * the value of the normal reference card used in byte 0x82 is set to 0b11 (3). 362 */ 363 #define SPD_LP4_LPDIMM_HEIGHT 0x080 364 #define SPD_LP4_LPDIMM_HEIGHT_REV(r) bitx8(r, 7, 5) 365 #define SPD_LP4_LPDIMM_HEIGHT_MM(r) bitx8(r, 4, 0) 366 #define SPD_LP4_LPDIMM_HEIGHT_LT15MM 0 367 #define SPD_LP4_LPDIMM_HEIGHT_BASE 15 368 369 /* 370 * S4.1.2 LP-DIMM: Module Maximum Thickness. These measure thicknesses in mm, 371 * with zero value meaning less than or equal to 1mm. 372 */ 373 #define SPD_LP4_LPDIMM_THICK 0x081 374 #define SPD_LP4_LPDIMM_THICK_BACK(r) bitx8(r, 7, 4) 375 #define SPD_LP4_LPDIMM_THICK_FRONT(r) bitx8(r, 3, 0) 376 #define SPD_LP4_LPDIMM_THICK_BASE 1 377 378 /* 379 * S4.1.3 LP-DIMM: Reference Raw Card Used. Bit 7 is used as basically another 380 * bit for bits 4-0. We do not define each meaning of these bit combinations in 381 * this header, that is left for tables in the library. When bits 6:5 are 0b11 382 * (3) then we must add in the reference card value in byte 0x80 to bits 6:5. 383 */ 384 #define SPD_LP4_LPDIMM_REF 0x082 385 #define SPD_LP4_LPDIMM_REF_EXT(r) bitx8(r, 7, 7) 386 #define SPD_LP4_LPDIMM_REF_REV(r) bitx8(r, 6, 5) 387 #define SPD_LP4_LPDIMM_REV_USE_HEIGHT 3 388 #define SPD_LP4_LPDIMM_REF_CARD(r) bitx8(r, 4, 0) 389 390 /* 391 * S4.1.5 LP-DIMM: CRC. Like DDR4, this is the CRC for the upper page. However, 392 * it is only defined on a per-Annex basis. 393 */ 394 #define SPD_LP4_BLK1_CRC_START 0x80 395 #define SPD_LP4_BLK1_CRC_LSB 0xfe 396 #define SPD_LP4_BLK1_CRC_MSB 0xff 397 398 #ifdef __cplusplus 399 } 400 #endif 401 402 #endif /* _SPD_LP4_H */ 403