1 /* 2 * Copyright 2014-2017 Cavium, Inc. 3 * The contents of this file are subject to the terms of the Common Development 4 * and Distribution License, v.1, (the "License"). 5 * 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the License at available 9 * at http://opensource.org/licenses/CDDL-1.0 10 * 11 * See the License for the specific language governing permissions and 12 * limitations under the License. 13 */ 14 15 #ifndef _SHMEM_H 16 #define _SHMEM_H 17 18 #include "bcmtype.h" 19 #include "5706_reg.h" 20 #include "license.h" 21 22 23 24 /* This structure will be located at the beginning of the MCP scratchpad. 25 * All firmwares need to be compiled to specify a starting address 26 * (> 0x08000010). 27 */ 28 typedef struct _shm_hdr_t 29 { 30 u32_t shm_hdr_signature; 31 #define SHM_ADDR_SIGN_MASK 0xffff0000 32 #define SHM_ADDR_SIGNATURE 0x53530000 33 /* The dword count is meaningful only for version 0x2 or after */ 34 #define SHM_ADDR_DWORD_SIZE_MASK 0xff00 35 #define SHM_ADDR_HDR_VER_MASK 0xff 36 #define SHM_ADDR_HDR_CURR_VER 0x1 37 #define SHM_ADDR_HDR_FIXED_LEN_VER 0x1 /* version 0 & 1 uses fixed length of SHM_ADDR_HDR_FIXED_LEN_SIZE (0x10) */ 38 #define SHM_ADDR_HDR_FIXED_LEN_SIZE 0x10 39 u32_t shm_addr[2]; 40 /* The address value is the host view address. The first one is 41 * for primary port, and the second one is for the secondary 42 * port (applicable in Xinan). We don't know if the shared 43 * memory will be part of the MCP scratchpad, thus, it is safer 44 * to show the host view and let firmware to calculate the CPU 45 * view. 46 */ 47 u32_t reserved; 48 } shm_hdr_t; 49 50 51 52 /* This value (in milliseconds) determines the frequency of the driver 53 * issuing the PULSE message code. The firmware monitors this periodic 54 * pulse to determine when to switch to an OS-absent mode. */ 55 #define DRV_PULSE_PERIOD_MS 250 56 57 /* This value (in milliseconds) determines how long the driver should 58 * wait for an acknowledgement from the firmware before timing out. Once 59 * the firmware has timed out, the driver will assume there is no firmware 60 * running and there won't be any firmware-driver synchronization during a 61 * driver reset. */ 62 #define FW_ACK_TIME_OUT_MS 50 63 64 /* This value (in usec) is the period before which the BIOS can ask us 65 * to disassociate the primary MAC address when checking on license. The 66 * entire handshake must be complete within this time. */ 67 #define HWKEY_SKIP_MAC_TIMEOUT_US 10000000 /* OEM specific */ 68 69 70 typedef struct _drv_fw_mb_t 71 { 72 u32_t drv_reset_signature; 73 #define DRV_RESET_SIGNATURE 0x47495352 74 #define BIOS_SIGNATURE 0x534f4942 75 /* During BIOS POST, this field will also be used for handshake 76 * of challenge-response with the BIOS to confirm its intent. 77 * The details of the challenge-response is defined in the 78 * implementation. */ 79 80 u32_t drv_mb; 81 #define DRV_MSG_CODE 0xff000000 82 #define DRV_MSG_CODE_RESET 0x01000000 83 #define DRV_MSG_CODE_UNLOAD 0x02000000 84 #define DRV_MSG_CODE_SHUTDOWN 0x03000000 85 #define DRV_MSG_CODE_SUSPEND_WOL 0x04000000 86 #define DRV_MSG_CODE_FW_TIMEOUT 0x05000000 87 #define DRV_MSG_CODE_UNUSED 0x06000000 88 #define DRV_MSG_CODE_DIAG 0x07000000 89 #define DRV_MSG_CODE_VALIDATE_KEY 0x08000000 90 #define DRV_MSG_CODE_SUSPEND_NO_WOL 0x09000000 91 #define DRV_MSG_CODE_GET_CURR_KEY 0x0a000000 92 #define DRV_MSG_CODE_UNLOAD_LNK_DN 0x0b000000 93 #define DRV_MSG_CODE_FIO_ACCESS 0x0c000000 94 #define DRV_MSG_CODE_KEEP_VLAN_UPDATE 0x0d000000 95 #define DRV_MSG_CODE_CMD_SET_LINK 0x10000000 96 #define DRV_MSG_CODE_CMD_REMOTE_PHY_MDIO 0x40000000 97 #define BIOS_MSG_CODE_HANDSHAKE 0xff000000 /* OEM specific */ 98 99 #define DRV_MSG_DATA 0x00ff0000 100 #define DRV_MSG_DATA_WAIT0 0x00010000 101 #define DRV_MSG_DATA_WAIT1 0x00020000 102 #define DRV_MSG_DATA_WAIT2 0x00030000 103 #define DRV_MSG_DATA_WAIT3 0x00040000 104 #define DRV_MSG_DATA_WAIT_RESET 0x00050000 105 #define DRV_MSG_DATA_WAIT4 0x00060000 106 /* Used by DRV_MSG_CODE_VALIDATE_KEY command */ 107 #define DRV_MSG_DATA_MANUF_KEY 0x00010000 108 #define DRV_MSG_DATA_UPGRADE_KEY 0x00020000 109 /* Used by BIOS_MSG_CODE_HANDSHAKE command */ 110 #define BIOS_MSG_DATA_REQ 0x00010000 /* OEM specific */ 111 #define BIOS_MSG_DATA_CONFIRM 0x00020000 /* OEM specific */ 112 /* Used by BIOS_MSG_CODE_HANDSHAKE command and... 113 The VIRT_*_MAC command requires two arguments in mb_args[]. 114 The top 16 bit of the first argument needs to be 115 VIRT_MAC_SIGNATURE. The remaining six bytes (two from first 116 argument, four from the second one) will be the MAC address. 117 However, if all F's are used as MAC, boot code will treat 118 this as reverting back to the original MAC in the NVRAM. 119 */ 120 #define BIOS_MSG_DATA_USE_VIRT_PRIM_MAC 0x00030000 /* OEM specific */ 121 #define BIOS_MSG_DATA_USE_VIRT_ISCSI_MAC 0x00040000 /* OEM specific */ 122 /* Used by DRV_MSG_CODE_FIO_ACCESS command */ 123 #define DRV_MSG_DATA_FIO_READ 0x00000000 124 #define DRV_MSG_DATA_FIO_WRITE 0x00010000 125 126 #define DRV_MSG_SEQ 0x0000ffff 127 128 u32_t fw_mb; 129 #define FW_SIGN_PRESERVE_MEMORY 0x55aa5a5a 130 #define FW_MSG_ACK 0x0000ffff 131 #define FW_MSG_STATUS_MASK 0x00ff0000 132 #define FW_MSG_STATUS_OK 0x00000000 133 #define FW_MSG_STATUS_FAILURE 0x00ff0000 134 #define FW_MSG_STATUS_INVALID_ARGS 0x00010000 135 #define FW_MSG_STATUS_DRV_PRSNT 0x00020000 136 /* This "signature" is used to preserve memory content from 137 * the hard reset issued by the boot code. 138 */ 139 140 u32_t link_status; 141 /* See netlink.h for bit definitions */ 142 #define FW_LINK_STATUS_BUSY 0x0005A000 143 #define FW_LINK_STATUS_CABLE_SENSE_MASK 0x40000000 144 #define FW_LINK_STATUS_SW_TIMER_EVENT_MASK 0x80000000 145 146 u32_t drv_pulse_mb; 147 #define DRV_PULSE_SEQ_MASK 0x00007fff 148 #define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000 149 /* The system time is in the format of 150 * (year-2001)*12*32 + month*32 + day. */ 151 #define DRV_PULSE_ALWAYS_ALIVE 0x00008000 152 /* Indicate to the firmware not to go into the 153 * OS absent when it is not getting driver pulse. 154 * This is used for debugging as well for PXE(MBA). */ 155 156 u32_t mb_args[2]; 157 /* This can be used to pass arguments to handshake with 158 * firmware. */ 159 160 u32_t reserved[1]; 161 } drv_fw_mb_t; 162 163 164 165 typedef struct _shared_hw_cfg_t 166 { 167 u8_t part_num[16]; /* Up to 16 bytes of NULL-terminated string */ 168 u32_t power_dissipated; 169 #define SHARED_HW_CFG_POWER_STATE_D3_MASK 0xff000000 170 #define SHARED_HW_CFG_POWER_STATE_D2_MASK 0xff0000 171 #define SHARED_HW_CFG_POWER_STATE_D1_MASK 0xff00 172 #define SHARED_HW_CFG_POWER_STATE_D0_MASK 0xff 173 u32_t power_consumed; 174 u32_t config; 175 #define SHARED_HW_CFG_DESIGN_NIC 0 176 #define SHARED_HW_CFG_DESIGN_LOM 0x1 177 #define SHARED_HW_CFG_PORT_SWAP 0x2 /* Xinan only */ 178 #define SHARED_HW_CFG_VAUX_OVERDRAW 0x4 179 #define SHARED_HW_CFG_UMP_USE_MII 0 /* TetonII */ 180 #define SHARED_HW_CFG_UMP_USE_RMII 0x8 /* TetonII */ 181 #define SHARED_HW_CFG_WOL_ENABLE_BEACON 0x10 /* TetonII, on by hw default */ 182 #define SHARED_HW_CFG_PHY_FIBER_2_5G 0x20 /* TetonII/Xinan, off (1G only) by default */ 183 #define SHARED_HW_CFG_BACKPLANE_APP 0x40 /* TetonII/Xinan fiber */ 184 #define SHARED_HW_CFG_CRS_DV_SRC_SELECT_RXDV 0 185 #define SHARED_HW_CFG_CRS_DV_SRC_SELECT_CRS 0x80 /* TetonII B0 and after */ 186 #define SHARED_HW_CFG_LED_MODE_SHIFT_BITS 8 /* Teton/TetonII only */ 187 #define SHARED_HW_CFG_LED_MODE_MASK 0x700 /* Teton/TetonII only */ 188 #define SHARED_HW_CFG_LED_MODE_MAC 0 /* Teton/TetonII only */ 189 #define SHARED_HW_CFG_LED_MODE_GPHY1 0x100 /* Teton/TetonII only */ 190 #define SHARED_HW_CFG_LED_MODE_GPHY2 0x200 /* Teton/TetonII only */ 191 #define SHARED_HW_CFG_LED_MODE_GPHY3 0x300 /* Teton/TetonII only */ 192 #define SHARED_HW_CFG_LED_MODE_GPHY4 0x400 /* Teton/TetonII only */ 193 #define SHARED_HW_CFG_LED_MODE_GPHY5 0x500 /* Teton/TetonII only */ 194 #define SHARED_HW_CFG_LED_MODE_GPHY6 0x600 /* Teton/TetonII only */ 195 #define SHARED_HW_CFG_LED_MODE_GPHY7 0x700 /* Teton/TetonII only */ 196 #define SHARED_HW_CFG_UMP_PHY_TIMING_ENABLE 0x800 /* TetonII B0 and after */ 197 #define SHARED_HW_CFG_UMP_PHY_TIMING_DISABLE 0 /* TetonII B0 and after */ 198 /* Select a GPIO to determine what mgmt fw to run, GPIO1 for ignore */ 199 #define SHARED_HW_CFG_MFW_CHOICE_SHIFT_BITS 12 200 #define SHARED_HW_CFG_MFW_CHOICE_GPIO_MASK 0x7000 /* Teton/TetonII only */ 201 #define SHARED_HW_CFG_MFW_CHOICE_IGNORE 0x0000 /* Teton/TetonII only */ 202 #define SHARED_HW_CFG_MFW_CHOICE_UNUSED1 0x1000 /* Teton/TetonII only */ 203 #define SHARED_HW_CFG_MFW_CHOICE_UNUSED2 0x2000 /* Teton/TetonII only */ 204 #define SHARED_HW_CFG_MFW_CHOICE_GPIO3 0x3000 /* Teton/TetonII only */ 205 #define SHARED_HW_CFG_MFW_CHOICE_GPIO4 0x4000 /* Teton/TetonII only */ 206 #define SHARED_HW_CFG_MFW_CHOICE_GPIO5 0x5000 /* Teton/TetonII only */ 207 #define SHARED_HW_CFG_MFW_CHOICE_GPIO6 0x6000 /* Teton/TetonII only */ 208 #define SHARED_HW_CFG_MFW_CHOICE_GPIO7 0x7000 /* Teton/TetonII only */ 209 #define SHARED_HW_CFG_MFW_CHOICE_MASK 0x7000 /* Xinan only */ 210 #define SHARED_HW_CFG_MFW_CHOICE_ANY 0x0000 /* Xinan only */ 211 #define SHARED_HW_CFG_MFW_CHOICE_NCSI 0x1000 /* Xinan only */ 212 #define SHARED_HW_CFG_MFW_CHOICE_UMP 0x2000 /* Xinan only */ 213 #define SHARED_HW_CFG_MFW_CHOICE_IPMI 0x3000 /* Xinan only */ 214 #define SHARED_HW_CFG_MFW_CHOICE_SPIO4_NCSI0_IPMI1 0x4000 /* Xinan only */ 215 #define SHARED_HW_CFG_MFW_CHOICE_SPIO4_UMP0_IPMI1 0x5000 /* Xinan only */ 216 #define SHARED_HW_CFG_MFW_CHOICE_SPIO4_NCSI0_UMP1 0x6000 /* Xinan only */ 217 #define SHARED_HW_CFG_MFW_CHOICE_RESERVED 0x7000 /* Xinan only */ 218 #define SHARED_HW_CFG_GIG_LINK_ON_VAUX 0x8000 219 #define SHARED_HW_CFG_LED_APP_MASK 0x30000 /* TetonII fiber (A0 and B0) only */ 220 #define SHARED_HW_CFG_LED_APP_INDEPENDENT 0x00000 /* TetonII fiber (A0 and B0) only */ 221 #define SHARED_HW_CFG_LED_APP_MULTI_COLOR 0x10000 /* TetonII fiber (A0 and B0) only */ 222 #define SHARED_HW_CFG_LED_APP_ALL_TIED 0x20000 /* TetonII fiber (A0 and B0) only */ 223 #define SHARED_HW_CFG_DUAL_MAC_MASK 0x30000 /* Xinan only */ 224 #define SHARED_HW_CFG_DUAL_MAC_BOTH 0x00000 /* Xinan only */ 225 #define SHARED_HW_CFG_DUAL_MAC_RESERVED 0x10000 /* Xinan only */ 226 #define SHARED_HW_CFG_DUAL_MAC_HIDE_FN1 0x20000 /* Xinan only */ 227 #define SHARED_HW_CFG_DUAL_MAC_INVALID 0x30000 /* Xinan only */ 228 #define SHARED_HW_CFG_PCIE_GEN2_ENABLE 0x40000 /* Xinan only */ 229 #define SHARED_HW_CFG_SMBUS_TIMING_100KHZ 0x0 /* Xinan only */ 230 #define SHARED_HW_CFG_SMBUS_TIMING_400KHZ 0x80000 /* Xinan only */ 231 #define SHARED_HW_CFG_PREVENT_PCIE_L1_ENTRY 0x100000 /* Xinan only */ 232 #define SHARED_HW_CFG_DUAL_MEDIA_CFG_MASK 0xe00000 /* Xinan only: reserved for future support */ 233 #define SHARED_HW_CFG_NO_LINK_FLAP 0x1000000 /* Xinan copper AN only */ 234 #define SHARED_HW_CFG_DUAL_MEDIA_OVERRIDE 0x2000000 /* Xinan only: reserved for future support */ 235 #define SHARED_HW_CFG_GEN2_TX_PREEMP_MASK 0xf0000000 /* Xinan only */ 236 #define SHARED_HW_CFG_GEN2_TX_PREEMP_HW 0x00000000 /* Xinan only: HW and 0_0DB are swapped in hw register */ 237 #define SHARED_HW_CFG_GEN2_TX_PREEMP_0_0DB 0xc0000000 /* Xinan only: HW and 0_0DB are swapped in hw register */ 238 #define SHARED_HW_CFG_GEN2_TX_PREEMP_3_5DB 0xa0000000 /* Xinan only */ 239 #define SHARED_HW_CFG_GEN2_TX_PREEMP_6_0DB 0xe0000000 /* Xinan only */ 240 u32_t config2; 241 #define SHARED_HW_CFG2_NVM_SIZE_MASK 0xfff000 242 u32_t shared_eco_ctl; 243 /* The bit definitions below are for TetonII only */ 244 #define SHARED_ECO_CTL_ECO203_EPB_0x78_BIT02 0x4 245 #define SHARED_ECO_CTL_ECO204_EPB_0x78_BIT31 0x80000000 246 #define SHARED_ECO_CTL_ECO206_EPB_0x78_BIT03 0x8 247 #define SHARED_ECO_CTL_ECO207_EPB_0x48_BIT24 0x100 /* Need to shift 16 bits to left */ 248 #define SHARED_ECO_CTL_EPB_0x48_SHIFT_BITS 16 /* Need to shift 16 bits to left */ 249 #define SHARED_ECO_CTL_ECO208_EPB_0x7C_BIT30 0x40000000 250 #define SHARED_ECO_CTL_ECO209_EPB_0x7C_BIT24 0x1000000 251 #define SHARED_ECO_CTL_ECO210_EPB_0x78_BIT26 0x4000000 252 #define SHARED_ECO_CTL_EPB_0x78_MASK (SHARED_ECO_CTL_ECO203_EPB_0x78_BIT02 | \ 253 SHARED_ECO_CTL_ECO206_EPB_0x78_BIT03 | \ 254 SHARED_ECO_CTL_ECO210_EPB_0x78_BIT26 | \ 255 SHARED_ECO_CTL_ECO204_EPB_0x78_BIT31) 256 #define SHARED_ECO_CTL_EPB_0x7C_MASK (SHARED_ECO_CTL_ECO209_EPB_0x7C_BIT24 | \ 257 SHARED_ECO_CTL_ECO208_EPB_0x7C_BIT30) 258 #define SHARED_ECO_CTL_EPB_0x48_MASK (SHARED_ECO_CTL_ECO207_EPB_0x48_BIT24) 259 u32_t reserved[1]; /* Any common info to all ports */ 260 } shared_hw_cfg_t; 261 262 263 264 265 #define PORT_HW_CFG_RESERVED_WORD_CNT 6 266 typedef struct _port_hw_cfg_t 267 { 268 /* Fields below are port specific (in anticipation of dual port devices */ 269 u32_t mac_upper; 270 #define PORT_HW_CFG_UPPERMAC_MASK 0xffff 271 u32_t mac_lower; 272 u32_t config; 273 #define PORT_HW_CFG_SERDES_TXCTL3_MASK 0xffff 274 #define PORT_HW_CFG_DEFAULT_LINK_MASK 0x1f0000 275 #define PORT_HW_CFG_DEFAULT_LINK_AN 0x0 276 #define PORT_HW_CFG_DEFAULT_LINK_SPEED_MASK 0x070000 277 #define PORT_HW_CFG_DEFAULT_LINK_1G 0x030000 278 #define PORT_HW_CFG_DEFAULT_LINK_2_5G 0x040000 279 #define PORT_HW_CFG_DEFAULT_LINK_AN_FALLBACK_MASK 0x100000 280 #define PORT_HW_CFG_DEFAULT_LINK_AN_1G_FALLBACK 0x130000 281 #define PORT_HW_CFG_DEFAULT_LINK_AN_2_5G_FALLBACK 0x140000 282 #define PORT_HW_CFG_DISABLE_PCIE_RELAX_ORDER 0x200000 /* Xinan only */ 283 #define PORT_HW_CFG_XI_LED_MODE_MASK 0x0f000000 /* Xinan only */ 284 #define PORT_HW_CFG_XI_LED_MODE_MAC 0x00000000 /* Xinan only */ 285 #define PORT_HW_CFG_XI_LED_MODE_PHY1 0x01000000 /* Xinan only */ 286 #define PORT_HW_CFG_XI_LED_MODE_PHY2 0x02000000 /* Xinan only */ 287 #define PORT_HW_CFG_XI_LED_MODE_PHY3 0x03000000 /* Xinan only */ 288 #define PORT_HW_CFG_XI_LED_MODE_MAC2 0x04000000 /* Xinan only */ 289 #define PORT_HW_CFG_XI_LED_MODE_PHY4 0x05000000 /* Xinan only */ 290 #define PORT_HW_CFG_XI_LED_MODE_PHY5 0x06000000 /* Xinan only */ 291 #define PORT_HW_CFG_XI_LED_MODE_PHY6 0x07000000 /* Xinan only */ 292 #define PORT_HW_CFG_XI_LED_MODE_MAC3 0x08000000 /* Xinan only */ 293 #define PORT_HW_CFG_XI_LED_MODE_PHY7 0x09000000 /* Xinan only */ 294 #define PORT_HW_CFG_XI_LED_MODE_PHY8 0x0a000000 /* Xinan only */ 295 #define PORT_HW_CFG_XI_LED_MODE_PHY9 0x0b000000 /* Xinan only */ 296 #define PORT_HW_CFG_XI_LED_MODE_MAC4 0x0c000000 /* Xinan only */ 297 #define PORT_HW_CFG_XI_LED_MODE_PHY10 0x0d000000 /* Xinan only */ 298 #define PORT_HW_CFG_XI_LED_MODE_PHY11 0x0e000000 /* Xinan only */ 299 #define PORT_HW_CFG_XI_LED_MODE_UNUSED 0x0f000000 /* Xinan only */ 300 u32_t l2_reserved[5]; 301 u32_t pci_id; /* Xinan only */ 302 #define PORT_HW_CFG_PCI_VENDOR_ID_MASK 0xffff0000 303 #define PORT_HW_CFG_PCI_DEVICE_ID_MASK 0x0ffff 304 u32_t pci_sub_id; /* Xinan only */ 305 #define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_MASK 0xffff0000 306 #define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_MASK 0x0ffff 307 u32_t iscsi_mac_upper; /* Upper 16 bits are always zeroes */ 308 u32_t iscsi_mac_lower; 309 u32_t backup_l2_mac_upper; /* Upper 16 bits are reserved, could be... */ 310 u32_t backup_l2_mac_lower; /* non-zeroes, used by OEM software (BIOS?) */ 311 u32_t port_eco_ctl; 312 313 /* The reserved fields must have values of 0 */ 314 /* Reserving fields for L4, L5, and iSCSI config for a specific port. */ 315 u32_t reserved[PORT_HW_CFG_RESERVED_WORD_CNT]; 316 317 } port_hw_cfg_t; 318 319 320 typedef struct _shared_feat_cfg_t 321 { 322 u32_t config; /* Any features common to all ports */ 323 #define SHARED_FEATURE_ENABLE_ISCSI_OFLD 0x1 /* For Linux of one OEM */ 324 #define SHARED_FEATURE_RESERVED_MASK 0xfffffffe 325 u32_t reserved[3]; 326 } shared_feat_cfg_t; 327 328 329 typedef struct _res_alloc_t 330 { 331 u32_t version; 332 #define RES_VER_STRING 'A' 333 #define RES_VER_STRING_MASK 0xff000000 334 #define RES_VER_STRING_SHIFT_BITS 24 335 /* These bits are maintained by BACS, no other SW/FW entity 336 * should manipulate them. They are consumed by TOE/iSCSI FW. */ 337 #define RES_RES_CFG_TOE_IPV6 (0x1 << 0) 338 #define RES_RES_CFG_ISCSI_IPV6 (0x1 << 1) 339 340 u32_t res_cfg; 341 /* Used for the users to decide what they want */ 342 #define RES_RES_CFG_VALID 0x01 343 /* Overloading with VPD FDO, should be okay. */ 344 #define RES_RES_CFG_DIAG 0x02 345 #define RES_RES_CFG_L2 0x04 346 #define RES_RES_CFG_ISCSI 0x08 347 #define RES_RES_CFG_RDMA 0x10 348 #define RES_RES_CFG_FCFS_DISABLED 0x80000000UL 349 u32_t enum_val; 350 /* Used for the base driver to figure out what to enumerate */ 351 #define RES_ENUM_VALID RES_RES_CFG_VALID 352 #define RES_ENUM_VAL_DIAG RES_RES_CFG_DIAG 353 #define RES_ENUM_VAL_L2 RES_RES_CFG_L2 354 #define RES_ENUM_VAL_ISCSI RES_RES_CFG_ISCSI 355 #define RES_ENUM_VAL_RDMA RES_RES_CFG_RDMA 356 #define RES_ENUM_VAL_UNUSED RES_RES_CFG_FCFS_DISABLED 357 358 u32_t conn_resource1; 359 #define RES_CONN_RDMA_MASK 0xffff0000 360 #define RES_CONN_TOE_MASK 0xffff 361 u32_t conn_resource2; 362 #define RES_CONN_ISCSI_MASK 0xffff0000 363 #define RES_CONN_ISER_MASK 0xffff 364 u32_t conn_resource3; 365 #define RES_CONN_UNUSED 0xffff0000 366 /* iSCSI pending tasks: range from 32 to 2048, relevent when 367 * RES_RES_CFG_ISCSI flag is set. */ 368 #define RES_CONN_ISCSI_PTASK_MASK 0xffff 369 u32_t conn_resource4; 370 371 } res_alloc_t; 372 373 374 #define PORT_FEAT_CFG_RESERVED_WORD_CNT 14 375 typedef struct _port_feat_cfg_t 376 { 377 u32_t config; 378 #define PORT_FEATURE_FORCE_EXPROM_ENABLED 0x00800000 379 #define PORT_FEATURE_WOL_ENABLED 0x01000000 380 #define PORT_FEATURE_MBA_ENABLED 0x02000000 381 #define PORT_FEATURE_MFW_ENABLED 0x04000000 382 #define PORT_FEATURE_RPHY_ENABLED 0x08000000 383 #define PORT_FEATURE_PCIE_CAPABILITY_MASK 0xf0 /* Xinan only */ 384 #define PORT_FEATURE_PCIE_CAPABILITY_ALL 0xf0 /* Xinan only */ 385 #define PORT_FEATURE_PCIE_CAPABILITY_ALL_DEF 0x0 /* Xinan only */ 386 #define PORT_FEATURE_BAR1_SIZE_MASK 0xf 387 #define PORT_FEATURE_BAR1_SIZE_DISABLED 0x0 388 #define PORT_FEATURE_BAR1_SIZE_64K 0x1 389 #define PORT_FEATURE_BAR1_SIZE_128K 0x2 390 #define PORT_FEATURE_BAR1_SIZE_256K 0x3 391 #define PORT_FEATURE_BAR1_SIZE_512K 0x4 392 #define PORT_FEATURE_BAR1_SIZE_1M 0x5 393 #define PORT_FEATURE_BAR1_SIZE_2M 0x6 394 #define PORT_FEATURE_BAR1_SIZE_4M 0x7 395 #define PORT_FEATURE_BAR1_SIZE_8M 0x8 396 #define PORT_FEATURE_BAR1_SIZE_16M 0x9 397 #define PORT_FEATURE_BAR1_SIZE_32M 0xa 398 #define PORT_FEATURE_BAR1_SIZE_64M 0xb 399 #define PORT_FEATURE_BAR1_SIZE_128M 0xc 400 #define PORT_FEATURE_BAR1_SIZE_256M 0xd 401 #define PORT_FEATURE_BAR1_SIZE_512M 0xe 402 #define PORT_FEATURE_BAR1_SIZE_1G 0xf 403 u32_t wol_config; 404 /* Default is used when driver sets to "auto" mode */ 405 #define FEATURE_WOL_DEFAULT_SHIFT_BITS 4 406 #define FEATURE_WOL_DEFAULT_MASK 0x30 407 #define FEATURE_WOL_DEFAULT_DISABLE 0 408 #define FEATURE_WOL_DEFAULT_MAGIC 0x10 409 #define FEATURE_WOL_DEFAULT_ACPI 0x20 410 #define FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI 0x30 411 #define FEATURE_WOL_LINK_SPEED_MASK 0xf 412 #define FEATURE_WOL_LINK_SPEED_AUTONEG 0 413 #define FEATURE_WOL_LINK_SPEED_10HALF 1 414 #define FEATURE_WOL_LINK_SPEED_10FULL 2 415 #define FEATURE_WOL_LINK_SPEED_100HALF 3 416 #define FEATURE_WOL_LINK_SPEED_100FULL 4 417 #define FEATURE_WOL_LINK_SPEED_1000HALF 5 418 #define FEATURE_WOL_LINK_SPEED_1000FULL 6 419 #define FEATURE_WOL_LINK_SPEED_2500HALF 7 420 #define FEATURE_WOL_LINK_SPEED_2500FULL 8 421 #define FEATURE_WOL_AUTONEG_LIMIT_MASK 0xc0 422 #define FEATURE_WOL_AUTONEG_LIMIT_10 0x80 423 #define FEATURE_WOL_AUTONEG_LIMIT_100 0x00 424 #define FEATURE_WOL_AUTONEG_LIMIT_1000 0x40 425 #define FEATURE_WOL_AUTONEG_ADVERTISE_1000 0x40 426 #define FEATURE_WOL_RESERVED_PAUSE_CAP 0x400 427 #define FEATURE_WOL_RESERVED_ASYM_PAUSE_CAP 0x800 428 u32_t mba_config; 429 #define FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT_BITS 0 430 #define FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT_BITS2 20 431 #define FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x400003 432 #define FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0 433 #define FEATURE_MBA_BOOT_AGENT_TYPE_RPL 1 434 #define FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 2 435 #define FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB 3 436 #define FEATURE_MBA_BOOT_AGENT_TYPE_FCOE 0x400000 437 #define FEATURE_MBA_BOOT_AGENT_TYPE_RESERVED_1 0x400001 438 #define FEATURE_MBA_BOOT_AGENT_TYPE_RESERVED_2 0x400002 439 #define FEATURE_MBA_BOOT_AGENT_TYPE_NONE 0x400003 440 #define FEATURE_MBA_LINK_SPEED_SHIFT_BITS 2 441 #define FEATURE_MBA_LINK_SPEED_MASK 0x3c 442 #define FEATURE_MBA_LINK_SPEED_AUTONEG 0 443 #define FEATURE_MBA_LINK_SPEED_10HALF 0x4 444 #define FEATURE_MBA_LINK_SPEED_10FULL 0x8 445 #define FEATURE_MBA_LINK_SPEED_100HALF 0xc 446 #define FEATURE_MBA_LINK_SPEED_100FULL 0x10 447 #define FEATURE_MBA_LINK_SPEED_1000HALF 0x14 448 #define FEATURE_MBA_LINK_SPEED_1000FULL 0x18 449 #define FEATURE_MBA_LINK_SPEED_2500HALF 0x1c 450 #define FEATURE_MBA_LINK_SPEED_2500FULL 0x20 451 #define FEATURE_MBA_SETUP_PROMPT_ENABLE 0x40 452 #define FEATURE_MBA_HOTKEY_CTRL_S 0 453 #define FEATURE_MBA_HOTKEY_CTRL_B 0x80 454 #define FEATURE_MBA_EXP_ROM_SIZE_SHIFT_BITS 8 455 #define FEATURE_MBA_EXP_ROM_SIZE_MASK 0xff00 456 #define FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0 457 #define FEATURE_MBA_EXP_ROM_SIZE_1K 0x100 458 #define FEATURE_MBA_EXP_ROM_SIZE_2K 0x200 459 #define FEATURE_MBA_EXP_ROM_SIZE_4K 0x300 460 #define FEATURE_MBA_EXP_ROM_SIZE_8K 0x400 461 #define FEATURE_MBA_EXP_ROM_SIZE_16K 0x500 462 #define FEATURE_MBA_EXP_ROM_SIZE_32K 0x600 463 #define FEATURE_MBA_EXP_ROM_SIZE_64K 0x700 464 #define FEATURE_MBA_EXP_ROM_SIZE_128K 0x800 465 #define FEATURE_MBA_EXP_ROM_SIZE_256K 0x900 466 #define FEATURE_MBA_EXP_ROM_SIZE_512K 0xa00 467 #define FEATURE_MBA_EXP_ROM_SIZE_1M 0xb00 468 #define FEATURE_MBA_EXP_ROM_SIZE_2M 0xc00 469 #define FEATURE_MBA_EXP_ROM_SIZE_4M 0xd00 470 #define FEATURE_MBA_EXP_ROM_SIZE_8M 0xe00 471 #define FEATURE_MBA_EXP_ROM_SIZE_16M 0xf00 472 #define FEATURE_MBA_MSG_TIMEOUT_SHIFT_BITS 16 473 #define FEATURE_MBA_MSG_TIMEOUT_MASK 0xf0000 474 #define FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT_BITS 20 475 #define FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x300000 476 #define FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0 477 #define FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x100000 478 #define FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x200000 479 #define FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x300000 480 #define FEATURE_MBA_BOOT_RETRY_MASK 0x3800000 /* bit 25 24 23*/ 481 #define FEATURE_MBA_BOOT_RETRY_SHIFT_BITS 23 482 u32_t bmc_common; 483 #define FEATURE_BMC_CMN_UNUSED_0 0x1 /* Used to be link override */ 484 #define FEATURE_BMC_CMN_ECHO_MODE_ENABLE 0x2 485 #define FEATURE_BMC_CMN_UNUSED_2 0x4 486 #define FEATURE_BMC_CMN_UMP_ID_ENABLE 0x8 /* Xinan only */ 487 #define FEATURE_BMC_CMN_UMP_ID_MASK 0x30 /* Xinan only */ 488 u32_t mba_vlan_cfg; 489 #define FEATURE_MBA_VLAN_TAG_MASK 0xffffL 490 #define FEATURE_MBA_VLAN_ENABLE 0x10000L 491 492 res_alloc_t resource; 493 494 u32_t smbus_config; 495 #define FEATURE_SMBUS_ENABLE 1 /* Obsolete */ 496 #define FEATURE_SMBUS_ADDR_MASK 0xfe 497 498 u32_t iscsib_basic_config; 499 #define FEATURE_ISCSIB_SKIP_TARGET_BOOT 1 500 501 union u_t 502 { 503 u32_t t2_epb_cfg; 504 #define T2_EPB_CFG_ENABLED 0x80000000 505 #define T2_EPB_CFG_OPT_L23 0x40000000 506 #define T2_EPB_CFG_OPT_NIC_D3 0x20000000 507 #define T2_EPB_CFG_OPT_INACTIVITY_CHK 0x10000000 508 #define T2_EPB_CFG_OPT_ACTIVITY_CHK 0x8000000 509 #define T2_EPB_CFG_OPT_PREP_L23 0x4000000 510 #define T2_EPB_CFG_IDLE_TMR_MS_MASK 0xffff 511 #define T2_EPB_FORCED_L1_VALUE 0xd8000bb8 512 #ifdef SOLARIS 513 } u1; 514 #else 515 } u; 516 #endif 517 518 u32_t reserved[PORT_FEAT_CFG_RESERVED_WORD_CNT]; 519 520 } port_feat_cfg_t; 521 522 523 524 #ifdef SOLARIS 525 typedef struct _bnx2shm_dev_info_t 526 #else 527 typedef struct _dev_info_t 528 #endif 529 { 530 u32_t signature; 531 #define DEV_INFO_SIGNATURE_MASK 0xffffff00 532 #define DEV_INFO_SIGNATURE 0x44564900 533 #define DEV_INFO_FEATURE_CFG_VALID 0x01 534 #define DEV_INFO_KEY_IN_EFFECT_MASK 0x06 535 #define DEV_INFO_MANUF_KEY_IN_EFFECT 0x02 536 #define DEV_INFO_UPGRADE_KEY_IN_EFFECT 0x04 537 #define DEV_INFO_NO_KEY_IN_EFFECT 0x06 538 #define DEV_INFO_DRV_ALWAYS_ALIVE 0x40 539 //#define DEV_INFO_SECONDARY_PORT 0x80 540 541 shared_hw_cfg_t shared_hw_config; 542 543 u32_t bc_rev; /* 8 bits each: Major, minor, build, 0x05 */ 544 545 port_hw_cfg_t port_hw_config; 546 547 u32_t virt_prim_mac_upper; /* Upper 16 bits are a signature */ 548 #define VIRT_MAC_SIGN_MASK 0xffff0000 549 #define VIRT_MAC_SIGNATURE 0x564d0000 550 u32_t virt_prim_mac_lower; 551 u32_t virt_iscsi_mac_upper; /* Upper 16 bits are a signature */ 552 u32_t virt_iscsi_mac_lower; 553 u32_t unused_a[4]; 554 555 /* Format revision: applies to shared and port features */ 556 u32_t format_rev; 557 #define FEATURE_FORMAT_REV_MASK 0xff000000 558 #define FEATURE_FORMAT_REV_ID ('A' << 24) 559 shared_feat_cfg_t shared_feature_config; 560 port_feat_cfg_t port_feature_config; 561 562 u32_t mfw_ver_ptr; 563 /* Valid only when mgmt FW is loaded (see CONDITION_MFW_RUN_MASK field). */ 564 #define MFW_VER_PTR_MASK 0x00ffffff 565 u32_t inv_table_ptr; 566 /* This is a scratchpad address for mgmt FW to use. */ 567 u32_t unused_b[(sizeof(port_feat_cfg_t))/4 - 2]; 568 569 #ifdef SOLARIS 570 } bnx2shm_dev_info_t; 571 #else 572 } dev_info_t; 573 #endif 574 575 576 577 typedef struct _bc_state_t 578 { 579 u32_t reset_type; 580 #define RESET_TYPE_SIGNATURE_MASK 0x0000ffff 581 #define RESET_TYPE_SIGNATURE 0x00005254 582 #define RESET_TYPE_NONE (RESET_TYPE_SIGNATURE |\ 583 0x00010000) 584 #define RESET_TYPE_PCI (RESET_TYPE_SIGNATURE |\ 585 0x00020000) 586 #define RESET_TYPE_VAUX (RESET_TYPE_SIGNATURE |\ 587 0x00030000) 588 #define RESET_TYPE_DRV_MASK DRV_MSG_CODE 589 #define RESET_TYPE_DRV_RESET (RESET_TYPE_SIGNATURE |\ 590 DRV_MSG_CODE_RESET) 591 #define RESET_TYPE_DRV_UNLOAD (RESET_TYPE_SIGNATURE |\ 592 DRV_MSG_CODE_UNLOAD) 593 #define RESET_TYPE_DRV_SHUTDOWN (RESET_TYPE_SIGNATURE |\ 594 DRV_MSG_CODE_SHUTDOWN) 595 #define RESET_TYPE_DRV_SUSPEND_NO_WOL (RESET_TYPE_SIGNATURE |\ 596 DRV_MSG_CODE_SUSPEND_NO_WOL) 597 #define RESET_TYPE_DRV_SUSPEND_WOL (RESET_TYPE_SIGNATURE |\ 598 DRV_MSG_CODE_SUSPEND_WOL) 599 #define RESET_TYPE_DRV_FW_TIMEOUT (RESET_TYPE_SIGNATURE |\ 600 DRV_MSG_CODE_FW_TIMEOUT) 601 #define RESET_TYPE_DRV_DIAG (RESET_TYPE_SIGNATURE |\ 602 DRV_MSG_CODE_DIAG) 603 #define RESET_TYPE_DRV_UNLOAD_LNK_DN (RESET_TYPE_SIGNATURE |\ 604 DRV_MSG_CODE_UNLOAD_LNK_DN) 605 #define RESET_TYPE_VALUE(msg_code) (RESET_TYPE_SIGNATURE |\ 606 (msg_code)) 607 u32_t state; 608 #define BC_STATE_ERR_MASK 0x0000ff00 609 #define BC_STATE_SIGN_MASK 0xffff0000 610 #define BC_STATE_SIGN 0x42530000 611 #define BC_STATE_BC1_START (BC_STATE_SIGN | 0x1) /* not used */ 612 #define BC_STATE_GET_NVM_CFG1 (BC_STATE_SIGN | 0x2) /* not used */ 613 #define BC_STATE_PROG_BAR (BC_STATE_SIGN | 0x3) /* not used */ 614 #define BC_STATE_INIT_VID (BC_STATE_SIGN | 0x4) /* not used */ 615 #define BC_STATE_GET_NVM_CFG2 (BC_STATE_SIGN | 0x5) /* not used */ 616 #define BC_STATE_APPLY_WKARND (BC_STATE_SIGN | 0x6) /* not used */ 617 #define BC_STATE_LOAD_BC2 (BC_STATE_SIGN | 0x7) /* not used */ 618 #define BC_STATE_GOING_BC2 (BC_STATE_SIGN | 0x8) /* not used */ 619 #define BC_STATE_GOING_DIAG (BC_STATE_SIGN | 0x9) /* not used */ 620 #define BC_STATE_RT_FINAL_INIT (BC_STATE_SIGN | 0x81) /* not used */ 621 #define BC_STATE_RT_WKARND (BC_STATE_SIGN | 0x82) /* not used */ 622 #define BC_STATE_RT_DRV_PULSE (BC_STATE_SIGN | 0x83) /* not used */ 623 #define BC_STATE_RT_FIOEVTS (BC_STATE_SIGN | 0x84) /* not used */ 624 #define BC_STATE_RT_DRV_CMD (BC_STATE_SIGN | 0x85) /* not used */ 625 #define BC_STATE_RT_LOW_POWER (BC_STATE_SIGN | 0x86) /* not used */ 626 #define BC_STATE_RT_SET_WOL (BC_STATE_SIGN | 0x87) /* not used */ 627 #define BC_STATE_RT_OTHER_FW (BC_STATE_SIGN | 0x88) /* not used */ 628 #define BC_STATE_RT_GOING_D3 (BC_STATE_SIGN | 0x89) /* not used */ 629 #define BC_STATE_ERROR_SET 0x8000 630 #define BC_STATE_ERR_BAD_VERSION (BC_STATE_SIGN | 0x8001) 631 #define BC_STATE_ERR_BAD_BC2_CRC (BC_STATE_SIGN | 0x8002) 632 #define BC_STATE_ERR_BC1_LOOP (BC_STATE_SIGN | 0x8003) 633 #define BC_STATE_ERR_UNKNOWN_CMD (BC_STATE_SIGN | 0x8004) 634 #define BC_STATE_ERR_DRV_DEAD (BC_STATE_SIGN | 0x8005) 635 #define BC_STATE_ERR_NO_RXP (BC_STATE_SIGN | 0x8006) 636 #define BC_STATE_ERR_TOO_MANY_RBUF (BC_STATE_SIGN | 0x8007) 637 #define BC_STATE_ERR_BAD_PCI_ID (BC_STATE_SIGN | 0x8008) 638 #define BC_STATE_ERR_FW_TIMEOUT (BC_STATE_SIGN | 0x8009) 639 #define BC_STATE_ERR_BAD_VPD_REQ (BC_STATE_SIGN | 0x800a) 640 #define BC_STATE_ERR_NO_LIC_KEY (BC_STATE_SIGN | 0x800b) 641 #define BC_STATE_ERR_NO_MGMT_FW (BC_STATE_SIGN | 0x800c) 642 #define BC_STATE_ERR_STACK_OVERFLOW (BC_STATE_SIGN | 0x800d) 643 #define BC_STATE_ERR_PCIE_LANE_DOWN (BC_STATE_SIGN | 0x800e) 644 #define BC_STATE_ERR_MEM_PARITY (BC_STATE_SIGN | 0x800f) 645 #define BC_STATE_ERR_WKARND_TOO_LONG (BC_STATE_SIGN | 0x8010) 646 u32_t condition; 647 #define CONDITION_INIT_POR 0x00000001 648 #define CONDITION_INIT_VAUX_AVAIL 0x00000002 649 #define CONDITION_INIT_PCI_AVAIL 0x00000004 650 /* The INIT_PCI_RESET is really a reset type, but defining as 651 * RESET_TYPE may break backward compatibility. */ 652 #define CONDITION_INIT_PCI_RESET 0x00000008 653 #define CONDITION_INIT_HD_RESET 0x00000010 /* Xinan only */ 654 #define CONDITION_DRV_PRESENT 0x00000100 655 #define CONDITION_LOW_POWER_LINK 0x00000200 656 #define CONDITION_CORE_RST_OCCURRED 0x00000400 /* Xinan only */ 657 #define CONDITION_UNUSED 0x00000800 /* Obsolete */ 658 #define CONDITION_BUSY_EXPROM 0x00001000 /* Teton/TetonII only */ 659 #define CONDITION_MFW_RUN_MASK 0x0000e000 660 #define CONDITION_MFW_RUN_UNKNOWN 0x00000000 661 #define CONDITION_MFW_RUN_IPMI 0x00002000 662 #define CONDITION_MFW_RUN_UMP 0x00004000 663 #define CONDITION_MFW_RUN_NCSI 0x00006000 664 #define CONDITION_MFW_RUN_NONE 0x0000e000 665 /* The followings are for Xinan in managing chip power on both ports */ 666 #define CONDITION_PM_STATE_MASK 0x00030000 /* Xinan only */ 667 #define CONDITION_PM_STATE_FULL 0x00030000 /* Xinan only */ 668 #define CONDITION_PM_STATE_PREP 0x00020000 /* Xinan only */ 669 #define CONDITION_PM_STATE_UNPREP 0x00010000 /* Xinan only */ 670 #define CONDITION_PM_RESERVED 0x00000000 /* Xinan only */ 671 672 #define CONDITION_WANT_FULL_POWER 0x00030000 /* Obsolete */ 673 #define CONDITION_WANT_PM_POWER 0x00010000 /* Can still have gigabit in LOMs */ /* Obsolete */ 674 #define CONDITION_WANT_ZERO_POWER 0x00000000 /* Obsolete */ 675 676 #define CONDITION_RXMODE_KEEP_VLAN 0x00040000 /* Mirroring RX_MODE_KEEP_VLAN bit in EMAC */ 677 #define CONDITION_DRV_WOL_ENABLED 0x00080000 /* Xinan only */ 678 #define CONDITION_PORT_DISABLED 0x00100000 /* Xinan only: meant to tell driver about port disabled */ 679 #define CONDITION_DRV_MAYBE_OUT 0x00200000 /* Xinan only for now */ 680 #define CONDITION_DPFW_DEAD 0x00400000 /* Xinan only for now */ 681 u32_t override; 682 #define OVERRIDE_SIGNATURE_MASK 0xffff0000 683 #define OVERRIDE_SIGNATURE 0x424f0000 684 #define OVERRIDE_MFW_CHOICE_MASK (CONDITION_MFW_RUN_MASK >> 13) // 0x7 685 #define OVERRIDE_MFW_DONTCARE (CONDITION_MFW_RUN_UNKNOWN >> 13) // 0x0 686 #define OVERRIDE_MFW_LOAD_IPMI (CONDITION_MFW_RUN_IPMI >> 13) // 0x1 687 #define OVERRIDE_MFW_LOAD_UMP (CONDITION_MFW_RUN_UMP >> 13) // 0x2 688 #define OVERRIDE_MFW_LOAD_NCSI (CONDITION_MFW_RUN_NCSI >> 13) // 0x3 689 #define OVERRIDE_MFW_LOAD_NONE (CONDITION_MFW_RUN_NONE >> 13) // 0x7 690 u32_t misc; 691 #define BC_MISC_PHY_ADDR_MASK 0x1f 692 u32_t wol_signature; 693 /* This is a simple signature value to indicate WOL being enabled 694 * on the next boot code invocation (reset). This allows driver to 695 * override the NVRAM setting for S5 WOL. */ 696 #define WOL_ENABLE_SIGNATURE 0x574f4c00 697 u32_t reserved[1]; 698 u32_t debug_cmd; /* Not used */ 699 #define BC_DBG_CMD_SIGNATURE_MASK 0xffff0000 700 #define BC_DBG_CMD_SIGNATURE 0x42440000 701 #define BC_DBG_CMD_LOOP_CNT_MASK 0xffff 702 #define BC_DBG_CMD_LOOP_INFINITE 0xffff 703 } bc_state_t; 704 705 /* This macro is used by to determine whether another 706 * software entity exists before making changes to the hardware. 707 * FW_TIMEOUT is included to handle the communication loss with the driver. 708 * It's better to assume that driver is still running to avoid messing up 709 * the driver in this case. */ 710 #define DRV_PRESENT(s) ( \ 711 ((shmem_region_t volatile *)s)->bc_state.condition & CONDITION_DRV_PRESENT) 712 713 #define PORT_DISABLED(s) ( \ 714 ((shmem_region_t volatile *)s)->bc_state.condition & CONDITION_PORT_DISABLED) 715 716 #ifdef DEBUG 717 #define SET_BC_STATE(p,s) \ 718 { \ 719 u32_t *ptr; \ 720 ptr = (u32_t *)&(((shmem_region_t volatile *)p)->bc_state.state); \ 721 if ((*ptr & BC_STATE_ERR_MASK) == 0) *ptr = s; \ 722 } 723 #else 724 #define SET_BC_STATE(p,s) 725 #endif 726 727 #define MGMTFW_STATE_WORD_SIZE 80 728 typedef struct _mgmtfw_state_t 729 { 730 /* Allocate 320 bytes for management firmware: still not known exactly 731 * how much IMD needs. */ 732 u32_t opaque[MGMTFW_STATE_WORD_SIZE]; 733 } mgmtfw_state_t; 734 735 typedef struct _fw_evt_mb_t 736 { 737 u32_t fw_evt_code_mb; 738 #define FW_EVT_CODE_LINK_STATUS_CHANGE_EVENT 0x00000001 739 #define FW_EVT_CODE_SW_TIMER_EXPIRATION_EVENT 0x00000000 740 741 u32_t fw_evt_data_mb[3]; 742 743 } fw_evt_mb_t; 744 745 746 typedef struct drv_fw_cap_mb 747 { 748 u32_t drv_ack_cap_mb; 749 #define CAPABILITY_SIGNATURE_MASK 0xFFFF0000 750 #define DRV_ACK_CAP_SIGNATURE 0x35450000 751 #define FW_ACK_DRV_SIGNATURE 0x52500000 752 u32_t fw_cap_mb; 753 #define FW_CAP_SIGNATURE 0xAA550000 754 755 #define FW_CAP_REMOTE_PHY_CAPABLE 0x00000001 756 #define FW_CAP_REMOTE_PHY_PRESENT 0x00000002 //bit 1 indicates absence or presence of remote phy HW 757 #define FW_CAP_UNUSED_BIT3 0x00000004 758 #define FW_CAP_MFW_CAN_KEEP_VLAN 0x00000008 759 #define FW_CAP_BC_CAN_UPDATE_VLAN 0x00000010 760 761 } drv_fw_cap_mb_t; 762 763 typedef struct remotephy 764 { 765 u32_t load_signature; 766 #define REMOTE_PHY_LOAD_SIGNATURE 0x5a5a5a5a 767 #define REMOTE_PHY_LEGACY_MODE_SIGNATURE 0xFFDEADFF 768 769 u32_t flags; 770 771 u32_t serdes_link_pref; 772 773 u32_t copper_phy_link_pref; 774 775 u32_t serdes_autoneg_pref; /* Xinan only, not supported in TetonII */ 776 u32_t copper_autoneg_pref; /* Xinan only, not supported in TetonII */ 777 /* The bit definitions follow those in netlink.h */ 778 779 u32_t link_backup; /* Teton II only; Xinan does not restart on driver load */ 780 781 } remotephy_t; 782 783 typedef struct _rt_param_t 784 { 785 /* These parameters are loaded with defaults by bootcode just before 786 * ack'ing WAIT1. Since there are two instances of shmem, if the 787 * parameter is shared for both ports, only the parameter of the 788 * first instance counts. */ 789 u32_t drv_timeout_val; /* Xinan only, in (val * 1.5) sec */ 790 u32_t dpfw_timeout_val; /* Xinan only, in timer_25mhz_free_run format */ 791 u32_t reserved[3]; 792 } rt_param_t; 793 794 /* Total size should be exactly 1k bytes */ 795 #define KEY_RSVD_DW_CNT ((52-sizeof(license_key_t))/4) 796 typedef struct _shmem_region_t 797 { 798 drv_fw_mb_t drv_fw_mb; /* 0x000 - 0x01f */ 799 #ifdef SOLARIS 800 bnx2shm_dev_info_t dev_info; /* 0x020 - 0x1bf */ 801 #else 802 dev_info_t dev_info; /* 0x020 - 0x1bf */ 803 #endif 804 bc_state_t bc_state; /* 0x1c0 - 0x1df */ 805 license_key_t fw_lic_key; /* 0x1e0 - 0x213 */ 806 mgmtfw_state_t mgmtfw_state; /* 0x214 - 0x353 */ 807 fw_evt_mb_t fw_evt_mb; /* 0x354 - 0x363 */ 808 drv_fw_cap_mb_t drv_fw_cap_mb; /* 0x364 - 0x36b */ 809 remotephy_t remotephy; /* 0x36c - 0x387 */ 810 u32_t dpfw_mb; /* 0x388 - 0x38b */ 811 rt_param_t rt_param; /* 0x38c - 0x39f */ 812 #define DPFW_MB_FW_ALIVE 0x00000001 813 /* Xinan only: Datapath firmware keeps writing 1 to it and 814 * BC keeps clearing it. */ 815 #ifdef SOLARIS 816 u32_t reserved[256 \ 817 - sizeof(drv_fw_mb_t)/4 \ 818 - sizeof(bnx2shm_dev_info_t)/4 \ 819 - sizeof(bc_state_t)/4 \ 820 - sizeof(license_key_t)/4 \ 821 - KEY_RSVD_DW_CNT \ 822 - sizeof(mgmtfw_state_t)/4 \ 823 - sizeof(fw_evt_mb_t)/4 \ 824 - sizeof(drv_fw_cap_mb_t)/4 \ 825 - sizeof(remotephy_t)/4 \ 826 - sizeof(u32_t)/4 \ 827 - sizeof(rt_param_t)/4 \ 828 - sizeof(license_key_t)/4 \ 829 - KEY_RSVD_DW_CNT \ 830 - 2 \ 831 ]; 832 #else 833 u32_t reserved[256 \ 834 - sizeof(drv_fw_mb_t)/4 \ 835 - sizeof(dev_info_t)/4 \ 836 - sizeof(bc_state_t)/4 \ 837 - sizeof(license_key_t)/4 \ 838 - KEY_RSVD_DW_CNT \ 839 - sizeof(mgmtfw_state_t)/4 \ 840 - sizeof(fw_evt_mb_t)/4 \ 841 - sizeof(drv_fw_cap_mb_t)/4 \ 842 - sizeof(remotephy_t)/4 \ 843 - sizeof(u32_t)/4 \ 844 - sizeof(rt_param_t)/4 \ 845 - sizeof(license_key_t)/4 \ 846 - KEY_RSVD_DW_CNT \ 847 - 2 \ 848 ]; 849 #endif 850 u32_t l1_wkarnd_dbg0; /* 0x3c4: used by TetonII BC only */ 851 u32_t l1_wkarnd_dbg1; /* 0x3c8: used by TetonII BC only */ 852 license_key_t drv_lic_key; /* 0x3cc - 0x3ff */ 853 } shmem_region_t; 854 855 856 #ifdef DOS16BIT_DRIVER 857 /* These will be generated in 5706_reg.h for 16-bit DOS driver */ 858 #define MCP_SCRATCH 0x160000 859 #define MCP_UNUSED_E 0x168000 860 /****************************************/ 861 #define MCP_SCRATCHPAD_START MCP_SCRATCH 862 #define MCP_SCRATCHPAD_END MCP_UNUSED_E 863 #else 864 #define MCP_SCRATCHPAD_START ROFFSET(mcp.mcp_scratch) 865 #define MCP_SCRATCHPAD_END ROFFSET(mcp.mcp_unused_e) 866 #endif 867 868 #define MCP_TETON_SCRATCH_SIZE 0x8000 869 870 /* Add the following to the original shared memory offset if the chip 871 * is 5708B0 or after, since it has 8kB more of scratchpad. 872 */ 873 #define MCP_SHMEM_5708B0_DELTA 0x2000 874 #define HOST_VIEW_SHMEM_BASE (MCP_SCRATCHPAD_START + \ 875 MCP_TETON_SCRATCH_SIZE - \ 876 sizeof(shmem_region_t)) /* 0x167c00 */ 877 #define SHMEM_BASE (HOST_VIEW_SHMEM_BASE - MCP_SCRATCHPAD_START) /* 0x7C00 */ 878 879 880 #endif /* _SHMEM_H */ 881 882