Home
last modified time | relevance | path

Searched refs:REG_PIO_WRITE64 (Results 1 – 6 of 6) sorted by relevance

/illumos-gate/usr/src/uts/common/io/nxge/npi/
H A Dnpi_fflp.c675 REG_PIO_WRITE64(handle, addr_reg, addr.value); in npi_fflp_fcram_entry_write()
679 REG_PIO_WRITE64(handle, data_reg, fcram_ptr->value[subarea]); in npi_fflp_fcram_entry_write()
769 REG_PIO_WRITE64(handle, addr_reg, addr.value); in npi_fflp_fcram_entry_read()
818 REG_PIO_WRITE64(handle, addr_reg, addr.value); in npi_fflp_fcram_entry_invalidate()
822 REG_PIO_WRITE64(handle, data_reg, hdr.value); in npi_fflp_fcram_entry_invalidate()
882 REG_PIO_WRITE64(handle, addr_reg, addr.value); in npi_fflp_fcram_subarea_write()
883 REG_PIO_WRITE64(handle, data_reg, data); in npi_fflp_fcram_subarea_write()
943 REG_PIO_WRITE64(handle, addr_reg, addr.value); in npi_fflp_fcram_subarea_read()
986 REG_PIO_WRITE64(handle, offset, sel.value); in npi_fflp_cfg_fcram_partition()
1024 REG_PIO_WRITE64(handle, offset, sel.value); in npi_fflp_cfg_fcram_partition_enable()
[all …]
/illumos-gate/usr/src/uts/common/io/hxge/
H A Dhpi_pfc.c176 REG_PIO_WRITE64(handle, offset, config.value); in hpi_pfc_set_config()
334 REG_PIO_WRITE64(handle, offset, table_entry.value); in hpi_pfc_cfg_vlan_table_clear()
358 REG_PIO_WRITE64(handle, offset, vlan_tbl_entry.value); in hpi_pfc_cfg_vlan_table_entry_clear()
381 REG_PIO_WRITE64(handle, offset, vlan_tbl_entry.value); in hpi_pfc_cfg_vlan_table_entry_set()
406 REG_PIO_WRITE64(handle, PFC_VLAN_CTRL, vlan_control.value); in hpi_pfc_cfg_vlan_control_set()
441 REG_PIO_WRITE64(handle, offset, addr.value); in hpi_pfc_set_mac_address()
442 REG_PIO_WRITE64(handle, moffset, mask.value); in hpi_pfc_set_mac_address()
462 REG_PIO_WRITE64(handle, offset, zaddr); in hpi_pfc_clear_mac_address()
463 REG_PIO_WRITE64(handle, moffset, zmask); in hpi_pfc_clear_mac_address()
477 REG_PIO_WRITE64(handle, offset, 0ULL); in hpi_pfc_clear_multicast_hash_table()
[all …]
H A Dhxge_pfc.h48 #define REG_PIO_WRITE64(handle, offset, value) \ macro
61 REG_PIO_WRITE64(handle, PFC_TCAM_CTRL, ctl)
67 REG_PIO_WRITE64(handle, PFC_TCAM_KEY0, key)
69 REG_PIO_WRITE64(handle, PFC_TCAM_KEY1, key)
71 REG_PIO_WRITE64(handle, PFC_TCAM_MASK0, mask)
73 REG_PIO_WRITE64(handle, PFC_TCAM_MASK1, mask)
H A Dhpi_vmac.c251 REG_PIO_WRITE64(handle, offset, HXGE_VMAC_RX_STAT_CLEAR); in hpi_vmac_clear_rx_int_stat()
262 REG_PIO_WRITE64(handle, offset, HXGE_VMAC_TX_STAT_CLEAR); in hpi_vmac_clear_tx_int_stat()
281 REG_PIO_WRITE64(handle, offset, value); in hpi_pfc_set_rx_int_stat_mask()
302 REG_PIO_WRITE64(handle, offset, value); in hpi_pfc_set_tx_int_stat_mask()
H A Dhxge_pfc.c891 REG_PIO_WRITE64(handle, offset, vlanid_group); in hxge_pfc_update_hw()
/illumos-gate/usr/src/uts/common/sys/nxge/
H A Dnxge_fflp_hw.h1095 #define REG_PIO_WRITE64(handle, offset, value) \ macro
1102 REG_PIO_WRITE64(handle, FFLP_TCAM_CTL_REG, ctl)
1109 REG_PIO_WRITE64(handle, FFLP_TCAM_KEY_0_REG, key)
1111 REG_PIO_WRITE64(handle, FFLP_TCAM_KEY_1_REG, key)
1113 REG_PIO_WRITE64(handle, FFLP_TCAM_KEY_2_REG, key)
1115 REG_PIO_WRITE64(handle, FFLP_TCAM_KEY_3_REG, key)
1117 REG_PIO_WRITE64(handle, FFLP_TCAM_MASK_0_REG, mask)
1119 REG_PIO_WRITE64(handle, FFLP_TCAM_MASK_1_REG, mask)
1121 REG_PIO_WRITE64(handle, FFLP_TCAM_MASK_2_REG, mask)
1123 REG_PIO_WRITE64(handle, FFLP_TCAM_MASK_3_REG, mask)